公开(公告)号：US20210193253A1

公开(公告)日：2021-06-24

申请号：US16849512

申请日：2020-04-15

Applicant: SK hynix Inc.

Inventor： Yo-Sep LEE ,  Dong-Ha LEE ,  Seon-Woo HWANG

IPC: G11C29/56 ,  G11C29/18 ,  G11C29/12 ,  H01L23/48 ,  H01L25/18

Abstract: A stacked semiconductor device including a plurality of semiconductor chips that are stacked and transfer signals through a plurality of through-electrodes, wherein at least one of the semiconductor chips comprises a first clock generation circuit suitable for generating first and second test clocks by dividing or buffering an external clock according to an operating information signal for indicating a high-speed test operation and a low-speed test operation; a first latch circuit suitable for latching a test control signal according to the first and second test clocks to generate first and second latched signals; and an input signal control circuit suitable for generating first and second internal control signals by re-latching the second latched signal according to the first test clock, and re-latching the first latched signal according to the second test clock.

公开(公告)号：US20200090733A1

公开(公告)日：2020-03-19

申请号：US16427418

申请日：2019-05-31

Applicant: SK hynix Inc.

Inventor： Yo-Sep LEE

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4076

Abstract: A memory includes: first to Nth areas refreshed based on first to Nth refresh control signals, respectively; a control signal generation circuit suitable for generating the second to Nth refresh control signals by sequentially delaying the first refresh control signal, and generating the first refresh control signal by delaying the Nth refresh control signal; an address counter suitable for changing a refresh address, corresponding to each round for activations of the first to Nth refresh control signals, based on the Nth refresh control signal; and a refresh stop circuit suitable for stopping a refresh operation when the round is repeated by a predetermined number.

公开(公告)号：US20150170733A1

公开(公告)日：2015-06-18

申请号：US14298581

申请日：2014-06-06

Applicant: SK hynix Inc.

Inventor： Yo-Sep LEE ,  Choung Ki SONG

IPC: G11C11/406

CPC classification number: G11C11/40615 ,  G11C7/02 ,  G11C11/406 ,  G11C11/4087

Abstract: A memory may include a plurality of word lines, a target address generation unit suitable for generating one or more target addresses by using a stored address, a refresh control section suitable for activating a refresh signal in response to a refresh command that is periodically inputted and periodically activating the refresh signal in a self-refresh mode, a target refresh control section suitable for activating a target refresh signal when the refresh signal is activated M times, wherein the M is a natural number, and deactivating the target refresh signal in the self-refresh mode and a row control section suitable for sequentially refreshing the plurality of word lines in response to the refresh signal and refreshing a word line corresponding to the target address in response to the refresh signal when the target refresh signal is activated.

Abstract translation: 存储器可以包括多个字线，适用于通过使用存储的地址来生成一个或多个目标地址的目标地址生成单元，适于根据周期性地输入的刷新命令来激活刷新信号的刷新控制部分，以及 在自刷新模式下周期性地激活刷新信号，当刷新信号被激活M次时适合于激活目标刷新信号的目标刷新控制部分，其中M是自然数，并且在自身中去激活目标刷新信号 - 刷新模式和行控制部分，其适于在响应于刷新信号顺序刷新多个字线并且当目标刷新信号被激活时响应于刷新信号刷新与目标地址相对应的字线。

公开(公告)号：US20200303030A1

公开(公告)日：2020-09-24

申请号：US16668129

申请日：2019-10-30

Applicant: SK hynix Inc.

Inventor： Yo-Sep LEE

IPC: G11C29/14 ,  H01L25/065 ,  H03K21/38 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G11C8/06 ,  G11C8/18 ,  G11C29/36 ,  G11C29/18

Abstract: A stacked semiconductor device includes semiconductor chips, each including a signal transfer circuit respectively transferring a command, an address, and a chip select signal to first to third through electrodes, and respectively transferring a test address and a chip ID to the second and third through electrodes according to a test control signal; a command reception circuit transferring a test command or a signal transferred from the first through electrode to an internal circuit when a signal transferred from the third through electrode is identical to the chip ID coincide with each other; and a test control circuit activating the test control signal according to deactivation of a test control signal of an upper chip, and generating the test command and the test address according to the test control signal.

公开(公告)号：US20180166117A1

公开(公告)日：2018-06-14

申请号：US15681595

申请日：2017-08-21

Applicant: SK hynix Inc.

Inventor： Hae-Rang CHOI ,  Youk-Hee KIM ,  Jae-Seung LEE ,  Mi-Hyeon JO ,  Dong-Jae LEE ,  Kyeong-Pil KANG ,  Sung-Soo CHI ,  Hyung-Sik WON ,  Hun-Sam JUNG ,  Yo-Sep LEE

IPC: G11C11/404 ,  G11C11/406

CPC classification number: G11C11/4045 ,  G11C11/404 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40622 ,  G11C11/40626 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/12015 ,  G11C29/40 ,  G11C29/4401 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/1202 ,  G11C2029/4402 ,  G11C2211/4068

Abstract: An operating method of a memory device including a plurality of memory cells may include: measuring data retention times of at least a portion of the plurality of memory cells; and optimizing a refresh operation on the plurality of memory cells using the measurement result.

公开(公告)号：US20160142058A1

公开(公告)日：2016-05-19

申请号：US14796933

申请日：2015-07-10

Applicant: SK hynix Inc.

Inventor： Yo-Sep LEE

IPC: H03K23/40 ,  H03K5/135

CPC classification number: H03K5/135 ,  H03K23/66 ,  H03K2005/00241 ,  H03K2005/00293

Abstract: A delay circuit may include a fine timing measurement unit suitable for measuring fine timing information on whether an input signal corresponds to the timing of any one of an even cycle or an odd cycle based on a clock, a coarse delay unit suitable for delaying the input signal whose fine timing has been measured by the fine timing measurement unit in synchronization with a frequency divided clock and outputting a delayed signal, and a fine timing application unit suitable for applying the fine timing information to the delayed signal of the coarse delay unit.

Abstract translation: 延迟电路可以包括适合于测量关于输入信号是否对应于基于时钟的偶数周期或奇数周期中的任一个的定时的精细定时信息的精细定时测量单元，适于延迟输入的粗延迟单元 信号，其精细定时由精细定时测量单元与分频时钟同步并输出延迟信号，精度定时应用单元适用于将精细定时信息应用于粗延迟单元的延迟信号。

公开(公告)号：US20150155023A1

公开(公告)日：2015-06-04

申请号：US14293649

申请日：2014-06-02

Applicant: SK hynix Inc.

Inventor： Yo-Sep LEE ,  Chang-Hyun KIM ,  Choung-Ki SONG

IPC: G11C8/18 ,  G11C8/06 ,  G11C8/10 ,  G11C8/08

CPC classification number: G11C8/18

Abstract: A semiconductor memory device includes a clock signal generation unit suitable for dividing an external clock signal to generate a first internal clock signal corresponding to odd number periods of the external clock signal and a second internal clock corresponding to even number periods, a first input unit suitable for receiving an external command signal and an external address signal in response to the first internal clock signal, a second input unit suitable for receiving the external command signal and the external address signal in response to the second internal clock signal, and an operation control unit suitable for enabling one of the first input unit and the second input unit and disabling the other of the first input unit and the second input unit, during a gear-down mode.

Abstract translation: 半导体存储器件包括：时钟信号生成单元，适于分割外部时钟信号以产生对应于外部时钟信号的奇数周期的第一内部时钟信号和对应于偶数周期的第二内部时钟;第一输入单元， 用于响应于第一内部时钟信号接收外部命令信号和外部地址信号，第二输入单元适于响应于第二内部时钟信号接收外部命令信号和外部地址信号;以及操作控制单元 适于在减速模式期间启用第一输入单元和第二输入单元中的一个并禁用第一输入单元和第二输入单元中的另一个。

公开(公告)号：US20140068171A1

公开(公告)日：2014-03-06

申请号：US13717470

申请日：2012-12-17

Applicant: SK HYNIX INC.

Inventor： Yo-Sep LEE

IPC: G06F13/16

CPC classification number: G06F13/1636 ,  Y02D10/14

Abstract: A refresh control circuit includes an internal chip information unit configured to provide internal chip information related to a retention characteristic of a memory cell, a mode information modification unit configured to output modified mode information based on the internal chip information, wherein the modified mode information represent a number of memory banks for refresh operation, and a selection signal activation unit configured to activate one or more of selection signals for selecting corresponding one or more of the memory banks in response to the modified mode information.

Abstract translation: 刷新控制电路包括：内部芯片信息单元，被配置为提供与存储单元的保持特性相关的内部芯片信息;模式信息修改单元，被配置为基于所述内部芯片信息输出修改模式信息，其中所述修改模式信息表示 用于刷新操作的多个存储体，以及选择信号激活单元，被配置为响应于修改的模式信息激活用于选择对应的一个或多个存储体的一个或多个选择信号。

公开(公告)号：US20140064009A1

公开(公告)日：2014-03-06

申请号：US13717944

申请日：2012-12-18

Applicant: SK HYNIX INC.

Inventor： Yo-Sep LEE

IPC: G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/40611 ,  G11C11/40618

Abstract: A memory device includes a plurality of memory blocks configured to be refreshed in response to respective refresh signals; a command decoder configured to decode an external input command to generate an internal refresh command; a refresh control unit configured to activate a first number of refresh signals corresponding to the first number of memory blocks when the internal refresh command is activated and a first mode is set, and to activate a second number of refresh signals corresponding to the second number of memory blocks when the internal refresh command is activated and a second mode is set, the second number being smaller than the first number; and an address counter configured to change the row address transferred to the memory blocks when a predetermined one of the refresh signals is activated.

Abstract translation: 存储器件包括多个存储器块，其被配置为响应于相应的刷新信号刷新; 命令解码器，被配置为解码外部输入命令以产生内部刷新命令; 刷新控制单元，被配置为当所述内部刷新命令被激活并且设置了第一模式时激活对应于所述第一数量的存储器块的第一数量的刷新信号，并且激活与所述第二数量的对应的第二数量的刷新信号 当内部刷新命令被激活并且设置了第二模式时，存储器块，第二个数字小于第一个数字; 以及地址计数器，被配置为当预定的刷新信号被激活时，改变传送到存储器块的行地址。

公开(公告)号：US20160225435A1

公开(公告)日：2016-08-04

申请号：US14732354

申请日：2015-06-05

Applicant: SK hynix Inc.

Inventor： Yo-Sep LEE

IPC: G11C11/406

CPC classification number: G11C11/40626

Abstract: A memory device may include a temperature sensor suitable for generating temperature information and a smart refresh circuit suitable for activating a smart refresh signal when an internal refresh signal is activated a set number of times, and controlling the set number based on the temperature information.

Abstract translation: 存储装置可以包括适于产生温度信息的温度传感器和适于在内部刷新信号被激活一定次数时激活智能刷新信号的智能刷新电路，并且基于温度信息来控制设定数量。