公开(公告)号：US11864476B2

公开(公告)日：2024-01-02

申请号：US17369725

申请日：2021-07-07

Applicant: SK hynix Inc.

Inventor： Byung Jick Cho ,  Yong Hun Sung ,  Ji Sun Han

IPC: G11C11/00 ,  H10N70/00 ,  G06F12/0831 ,  H10B63/00

CPC classification number: H10N70/841 ,  G06F12/0831 ,  H10B63/80 ,  H10N70/883 ,  H10N70/8845

Abstract: An electronic device comprises a semiconductor memory that includes: a first line; a second line disposed over the first line to be spaced apart from the first line; a variable resistance layer disposed between the first line and the second line; a selection element layer disposed between the first line and the variable resistance layer or between the second line and the variable resistance layer; and one or more electrode layers disposed over or under the selection element layer or disposed over and under the selection element layer, the one or more electrode layers being adjacent to the selection element layer, wherein each of the one or more electrode layers includes a first electrode layer and a second electrode layer, the second electrode layer including a second carbon layer containing nitrogen, the first electrode layer including a first carbon layer containing a lower concentration of nitrogen or containing no nitrogen.

公开(公告)号：US12069972B2

公开(公告)日：2024-08-20

申请号：US17391858

申请日：2021-08-02

Applicant: SK hynix Inc.

Inventor： Ji Sun Han

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/841 ,  H10B63/84 ,  H10N70/026 ,  H10N70/231 ,  H10N70/821

Abstract: A semiconductor device includes: a first electrode including a carbon layer; a second electrode; a variable resistance layer interposed between the first electrode and the second electrode; and a barrier layer interposed between the first electrode and the variable resistance layer, the barrier layer including nitrogen and carbon. A concentration of the nitrogen in the barrier layer is equal to or higher than that of the carbon in the barrier layer.

公开(公告)号：US12295273B2

公开(公告)日：2025-05-06

申请号：US18590813

申请日：2024-02-28

Applicant: SK hynix Inc.

Inventor： Myoung Sub Kim ,  Tae Hoon Kim ,  Beom Seok Lee ,  Seung Yun Lee ,  Hwan Jun Zang ,  Byung Jick Cho ,  Ji Sun Han

IPC: H10N70/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/20

Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.

公开(公告)号：US11950522B2

公开(公告)日：2024-04-02

申请号：US17847034

申请日：2022-06-22

Applicant: SK hynix Inc.

Inventor： Myoung Sub Kim ,  Tae Hoon Kim ,  Beom Seok Lee ,  Seung Yun Lee ,  Hwan Jun Zang ,  Byung Jick Cho ,  Ji Sun Han

IPC: H10N70/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/20

CPC classification number: H10N70/841 ,  H10B61/00 ,  H10B63/84 ,  H10N50/01 ,  H10N50/80 ,  H10N70/011 ,  H10N70/231

Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.

公开(公告)号：US11882775B2

公开(公告)日：2024-01-23

申请号：US17467084

申请日：2021-09-03

Applicant: SK hynix Inc.

Inventor： Ji Sun Han ,  Yong Hun Sung ,  Byung Jick Cho

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/883 ,  H10B63/80 ,  H10N70/011 ,  H10N70/841 ,  H10N70/8845

Abstract: An electronic device comprises a semiconductor memory that includes: a first line; a second line disposed over the first line to be spaced apart from the first line; a variable resistance layer disposed between the first line and the second line; a first electrode layer disposed between the first line and the variable resistance layer; and a first oxide layer disposed between the variable resistance layer and the first electrode layer. The first electrode layer includes a first carbon material doped with a first element, and the first oxide layer includes a first oxide of the first element.

公开(公告)号：US11430952B2

公开(公告)日：2022-08-30

申请号：US16984688

申请日：2020-08-04

Applicant: SK hynix Inc.

Inventor： Myoung Sub Kim ,  Tae Hoon Kim ,  Beom Seok Lee ,  Seung Yun Lee ,  Hwan Jun Zang ,  Byung Jick Cho ,  Ji Sun Han

IPC: H01L45/00 ,  H01L27/24 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.