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公开(公告)号：US11430952B2
公开(公告)日：2022-08-30
申请号：US16984688
申请日：2020-08-04
Applicant: SK hynix Inc.
Inventor： Myoung Sub Kim , Tae Hoon Kim , Beom Seok Lee , Seung Yun Lee , Hwan Jun Zang , Byung Jick Cho , Ji Sun Han
Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
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公开(公告)号：US11283017B2
公开(公告)日：2022-03-22
申请号：US16883770
申请日：2020-05-26
Applicant: SK hynix Inc.
Inventor： Myoung Sub Kim
Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include: a first variable resistance layer including antimony (Sb); a second variable resistance layer including antimony (Sb) with a content different from that of the first variable resistance layer, the second variable resistance layer having a crystallization speed different from that of the first variable resistance layer; and a first electrode interposed between the first variable resistance layer and the second variable resistance layer.
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3.发明授权Resistive memory device capable of preventing disturbance and method for manufacturing the same 有权能够防止干扰的电阻式存储装置及其制造方法公开(公告)号：US09054304B2
公开(公告)日：2015-06-09
申请号：US13791468
申请日：2013-03-08
Applicant: SK hynix Inc.
Inventor： Seung Yun Lee , Hae Chan Park , Myoung Sub Kim , Sung Bin Hong , Se Ho Lee , Jung Won Seo
CPC classification number: H01L45/1253 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/16 , H01L45/1683
Abstract: A resistive memory device capable of preventing disturbance is provided. The resistive memory device includes a lower electrode formed on a semiconductor substrate, a variable resistor disposed on the lower electrode, an upper electrode disposed on the variable resistor, and an interlayer insulating layer configured to insulate the variable resistor. The interlayer insulating layer may include an air-gap area in at least a portion thereof.
Abstract translation: 提供能够防止干扰的电阻式存储装置。 电阻式存储器件包括形成在半导体衬底上的下电极，设置在下电极上的可变电阻器，设置在可变电阻器上的上电极以及被配置为使可变电阻器绝缘的层间绝缘层。 层间绝缘层的至少一部分中可以包括气隙区域。
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4.发明授权公开(公告)号：US08917545B2
公开(公告)日：2014-12-23
申请号：US14183193
申请日：2014-02-18
Applicant: SK Hynix Inc.
Inventor： Myoung Sub Kim , Soo Gil Kim , Nam Kyun Park , Sung Cheoul Kim , Gap Sok Do , Joon Seop Sim , Hyun Jeong Lee
CPC classification number: H01L45/1675 , G11C13/0004 , G11C2013/008 , G11C2213/71 , H01L27/2409 , H01L27/249 , H01L45/06 , H01L45/1226 , H01L45/1246 , H01L45/126 , H01L45/144
Abstract: A semiconductor integrated circuit device, a method of manufacturing the same, and a method of driving the same are provided. The device includes a semiconductor substrate, an upper electrode extending from a surface of the semiconductor substrate; a plurality of switching structures extending from both sidewalls of the upper electrode in a direction parallel to the surface of the semiconductor substrate, and a phase-change material layer disposed between the plurality of switching structures and the upper electrode.
Abstract translation: 提供了一种半导体集成电路器件及其制造方法及其驱动方法。 该器件包括半导体衬底，从半导体衬底的表面延伸的上电极; 多个开关结构，其从与上述半导体基板的表面平行的方向从上述电极的两侧延伸;以及相变材料层，设置在上述多个开关结构体和上部电极之间。
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公开(公告)号：US12295273B2
公开(公告)日：2025-05-06
申请号：US18590813
申请日：2024-02-28
Applicant: SK hynix Inc.
Inventor： Myoung Sub Kim , Tae Hoon Kim , Beom Seok Lee , Seung Yun Lee , Hwan Jun Zang , Byung Jick Cho , Ji Sun Han
Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
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Patent Agency Ranking
公开(公告)号：US11950522B2
公开(公告)日：2024-04-02
申请号：US17847034
申请日：2022-06-22
Applicant: SK hynix Inc.
Inventor： Myoung Sub Kim , Tae Hoon Kim , Beom Seok Lee , Seung Yun Lee , Hwan Jun Zang , Byung Jick Cho , Ji Sun Han
CPC classification number: H10N70/841 , H10B61/00 , H10B63/84 , H10N50/01 , H10N50/80 , H10N70/011 , H10N70/231
Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
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公开(公告)号：US09236121B2
公开(公告)日：2016-01-12
申请号：US14158496
申请日：2014-01-17
Applicant: SK hynix Inc.
Inventor： Seung Yun Lee , Hae Chan Park , Myoung Sub Kim , Se Ho Lee
CPC classification number: G11C13/004 , G11C7/04 , G11C13/0004 , G11C13/0033 , G11C2013/008
Abstract: A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment unit suitable for adjusting a temperature of a memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result.
Abstract translation: 提供半导体存储装置及其温度控制方法。 半导体存储装置包括适于调节存储单元的温度的温度调节单元，以及温度调节单元，其适于感测温度调节单元的温度，将感测温度与参考温度范围进行比较，并且控制温度调节 基于比较结果在基准温度范围内调节其温度。
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公开(公告)号：US09111762B2
公开(公告)日：2015-08-18
申请号：US14098176
申请日：2013-12-05
Applicant: SK hynix Inc.
Inventor： Myoung Sub Kim
IPC: H01L29/06 , H01L21/265 , H01L29/417 , H01L29/66 , H01L29/78 , H01L29/08
CPC classification number: H01L29/06 , H01L21/265 , H01L21/26553 , H01L21/26586 , H01L29/0847 , H01L29/41741 , H01L29/66666 , H01L29/7827
Abstract: A semiconductor device includes a semiconductor substrate, a plurality of pillars vertically extending from the semiconductor substrate, each pillar including a groove formed in an upper surface thereof, a salicide layer formed to cover the upper surface and a lateral circumference of an upper end of each pillar and a lower electrode formed to cover an upper surface and a lateral surface of the salicide layer.
Abstract translation: 半导体器件包括半导体衬底，从半导体衬底垂直延伸的多个柱，每个柱包括形成在其上表面中的凹槽，形成为覆盖每个的上表面和上端的横向圆周的自对准层 柱和形成为覆盖所述自对准硅化物层的上表面和侧表面的下电极。
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公开(公告)号：US09818481B2
公开(公告)日：2017-11-14
申请号：US15434458
申请日：2017-02-16
Applicant: SK hynix Inc.
Inventor： Hae Chan Park , Myoung Sub Kim , Se Ho Lee , Seung Yun Lee
CPC classification number: G11C13/003 , G11C11/5678 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2013/0092 , G11C2213/15 , G11C2213/73
Abstract: A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal.
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公开(公告)号：US09613690B2
公开(公告)日：2017-04-04
申请号：US14043524
申请日：2013-10-01
Applicant: SK hynix Inc.
Inventor： Hae Chan Park , Myoung Sub Kim , Se Ho Lee , Seung Yun Lee
CPC classification number: G11C13/003 , G11C11/5678 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2013/0092 , G11C2213/15 , G11C2213/73
Abstract: A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal.
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