公开(公告)号：US20230057560A1

公开(公告)日：2023-02-23

申请号：US17572033

申请日：2022-01-10

Applicant: SK hynix Inc.

Inventor： Jun Yong SONG ,  Kang Hun KIM ,  Si Yun KIM

IPC: H01L23/00

Abstract: A semiconductor device includes a chip body; a passivation layer on the chip body; a lower dielectric layer on the passivation layer; a first re-distribution pad on the lower dielectric layer; an upper dielectric layer on the lower dielectric layer, the upper dielectric layer having a groove that exposes an upper surface of the first re-distribution pad; and a second re-distribution pad on the upper dielectric layer. An upper surface of the second re-distribution pad is positioned at a higher level than the upper surface of the first re-distribution pad.

公开(公告)号：US20240162176A1

公开(公告)日：2024-05-16

申请号：US18308891

申请日：2023-04-28

Applicant: SK hynix Inc.

Inventor： Kang Hun KIM ,  Si Yun KIM ,  Jun Yong SONG

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/16145

Abstract: A semiconductor package includes a bump interconnection structure. The semiconductor package includes a first lead and a second lead spaced apart from each other on a first substrate, a bump disposed to face the first lead in a second substrate, and a solder layer configured to connect the bump and the first lead. The first lead has a stair shape that ascends toward the second lead.

公开(公告)号：US20230230960A1

公开(公告)日：2023-07-20

申请号：US17835322

申请日：2022-06-08

Applicant: SK hynix Inc.

Inventor： Si Yun KIM ,  Kang Hun KIM ,  Jun Yong SONG

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/48 ,  H01L21/78 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/48227 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/02311

Abstract: A semiconductor device includes a chip body; a circuit layer over the chip body; an upper insulating layer over the circuit layer; a chip metal layer over the upper insulating layer, the chip metal layer including a pad portion; a passivation layer over the chip metal layer; a lower redistribution insulating layer over the passivation layer, the pad portion of the chip metal layer left exposed by the passivation layer and the lower redistribution insulating layer; a redistribution bonding interconnection over the lower redistribution insulating layer; and an upper redistribution insulating layer over the lower redistribution insulating layer. The redistribution bonding interconnection includes a pad connection portion electrically connected to the pad portion of the chip metal layer; a horizontal extension portion extending from the pad connection portion to a side surface of the chip body; a vertical extension portion disposed over the side surface of the chip body, the vertical extension portion extending downward from a side end portion of the horizontal extension portion; and a bonding portion disposed over the side surface of the chip body. The bonding portion is positioned at a lower end portion of the vertical extension portion.

公开(公告)号：US20230034877A1

公开(公告)日：2023-02-02

申请号：US17548205

申请日：2021-12-10

Applicant: SK hynix Inc.

Inventor： Jun Yong SONG ,  Kang Hun KIM ,  Si Yun KIM

IPC: H01L23/00

Abstract: Provided is a method of manufacturing a semiconductor device including a bump interconnect structure. In the method of manufacturing the semiconductor device, a first substrate including a connection pad is formed, and a bump including a solder layer and a metal post protruding from the solder layer are formed on the connection pad. A second substrate including a bump land may be formed. The first substrate may be disposed on the second substrate so that a protruding end of the metal post contacts the bump land, and the solder layer may be reflowed. Accordingly, it possible to interconnect the metal post to the bump land.

公开(公告)号：US20230154879A1

公开(公告)日：2023-05-18

申请号：US17717674

申请日：2022-04-11

Applicant: SK hynix Inc.

Inventor： Si Yun KIM ,  Kang Hun KIM ,  Jun Yong SONG

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/05 ,  H01L24/13 ,  H01L2924/3841 ,  H01L2224/1403 ,  H01L2224/1703 ,  H01L2224/16227 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/13147 ,  H01L2224/14133 ,  H01L2224/0613 ,  H01L24/06 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2924/014 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/1146 ,  H01L2224/11474 ,  H01L2224/0361 ,  H01L2224/11849 ,  H01L2224/81203 ,  H01L24/81

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, input and output (I/O) pads disposed at an upper portion of the semiconductor substrate, and first bump pillars disposed over the I/O pads. The first bump pillars are selectively arranged over some of the I/O pads in a first horizontal direction.

公开(公告)号：US20230154835A1

公开(公告)日：2023-05-18

申请号：US17715722

申请日：2022-04-07

Applicant: SK hynix Inc.

Inventor： Si Yun KIM ,  Kang Hun KIM ,  Jun Yong SONG

IPC: H01L23/498

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L24/48

Abstract: A semiconductor package includes a package substrate, a connection pad including a recessed portion disposed on one surface of the package substrate, and an insulating pattern disposed on the one surface of the package substrate to be spaced apart from the connection pad. The connection pad includes an outer sidewall, an inner sidewall in the recessed portion inclining in an inward direction from an upper portion, and a groove pattern formed on the inner sidewall.

公开(公告)号：US20230056222A1

公开(公告)日：2023-02-23

申请号：US17577196

申请日：2022-01-17

Applicant: SK hynix Inc.

Inventor： Kang Hun KIM ,  Si Yun KIM ,  Jun Yong SONG

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor package may be presented. The semiconductor package includes a first dielectric layer including a first surface and a second surface. First and second conductive lands are disposed on the first surface of the first dielectric layer. A first column formed by the first conductive lands and a second column formed by the second conductive lands are spaced apart from each other. Outer traces extend from the second conductive lands, and inner traces are disposed on the second surface of the first dielectric layer. Vias penetrate the first dielectric layer and respectively connect the first conductive lands to the inner traces. A semiconductor die is disposed on the first surface of the first dielectric layer.