公开(公告)号：US10936409B2

公开(公告)日：2021-03-02

申请号：US16199333

申请日：2018-11-26

Applicant: SK hynix Inc.

Inventor： Kang-Sub Kwak ,  Ki-Up Kim ,  Young-Jun Yoon

IPC: H03M13/11 ,  H03M13/15 ,  H03M13/19 ,  G06F11/10

Abstract: A memory system comprises: a memory cell array suitable for storing first data and a first parity, which is used to correct an error of the first data; and an error correcting circuit suitable for generating second data and a second parity, which includes bits obtained by correcting an error of the first parity and a bit obtained by correcting an error of a second sub-parity; wherein the error correcting circuit includes: a single error correction and double error detection (SECDED) parity generator suitable for generating a second pre-parity, which includes a first sub-parity and the second sub-parity; a syndrome decoder suitable for generating a first parity error flag and a first data error flag by decoding a syndrome; a SEC parity corrector suitable for correcting an error of the first parity based on the first parity error flag; a DED parity error detector suitable for generating a second sub-parity error flag based on an error information of the first data used to generate the second sub-parity; and a DED parity corrector suitable for correcting any error of the second sub-parity based on the second sub-parity error flag.

公开(公告)号：US09019789B2

公开(公告)日：2015-04-28

申请号：US13717466

申请日：2012-12-17

Applicant: SK Hynix Inc.

Inventor： Ki-Up Kim

IPC: G11C7/02 ,  G11C7/22 ,  G11C11/34 ,  G11C7/06 ,  G11C7/08 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C7/062 ,  G11C7/08 ,  G11C7/1048 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/4091 ,  G11C11/4096

Abstract: A semiconductor integrated circuit includes an input data line pair, a sense amplifier configured to sense and amplify data loaded in the input data line pair and transmit the amplified data to an output data line pair, in response to a control signal, and a sense amplification controller configured to sense an amplification level of the output data line pair, limit an activation period of a sense amplification enable signal, and output the limited signal as the control signal.

Abstract translation: 半导体集成电路包括输入数据线对，读出放大器，被配置为响应于控制信号，感测和放大加载在输入数据线对中的数据并将放大的数据发送到输出数据线对，以及感测放大 控制器，被配置为感测输出数据线对的放大电平，限制读出放大使能信号的激活周期，并输出限制信号作为控制信号。