-
公开(公告)号：US09054697B2
公开(公告)日：2015-06-09
申请号：US13890802
申请日：2013-05-09
Applicant: SK hynix Inc.
Inventor： Hae-Rang Choi , Yong-Ju Kim , Oh-Kyong Kwon , Kang-Sub Kwak , Jun-Yong Song , Hyeon-Cheon Seol
IPC: H03K19/23 , H03K19/003 , H03K19/08
CPC classification number: H03K19/0813 , H03K19/23
Abstract: A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.
Abstract translation: 多数决定电路包括：多数决定单元，被配置为将第一数据与第二数据进行比较，以确定第一数据和第二数据之一是否具有更多具有第一逻辑值的位; 以及偏移应用单元，被配置为控制多数决定单元，使得多数决定单元在第一数据中具有第一逻辑值的比特数等于具有第一逻辑值的比特数在 第二数据，如果偏移量是第一相位中的第一设定值，则第一数据具有具有第一逻辑值的更多位，并且如果偏移量是第二设定值，则判定第二数据具有第一逻辑值的更多位 第二阶段
-
公开(公告)号：US09018991B2
公开(公告)日：2015-04-28
申请号：US14106817
申请日：2013-12-15
Inventor： Hae-Rang Choi , Yong-Ju Kim , Oh-Kyong Kwon , Kang-Sub Kwak , Jun-Yong Song , Hyeon-Cheon Seol
CPC classification number: H03L7/0807 , H04L7/0337 , H04L7/044
Abstract: A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.
Abstract translation: 数据恢复电路可以包括适于使用数据时钟和边沿时钟对包括边缘数据的源数据进行采样的数据采样单元，适合于从数据采样单元输出的采样数据中提取边缘数据的数据提取单元，控制信号 适用于响应于边缘数据产生相位控制信号的多时钟单元，以及适于根据相位控制信号控制数据时钟和边沿时钟的相位的多时钟控制单元。
-
公开(公告)号：US11481127B2
公开(公告)日：2022-10-25
申请号：US16578660
申请日：2019-09-23
Applicant: SK hynix Inc.
Inventor： Kang-Sub Kwak
Abstract: A semiconductor memory device includes a memory region from which first data and second data are sequentially read, and a data output circuit suitable for selectively performing a reset operation on a data pad according to a logical relationship between the first and second data during an output disable period between a first output enable period corresponding to first output data and a second output enable period corresponding to second output data, when sequentially outputting the first and second output data corresponding to the first and second data through the data pad.
-
公开(公告)号：US10985307B2
公开(公告)日：2021-04-20
申请号：US16597542
申请日：2019-10-09
Applicant: SK hynix Inc.
Inventor： Kang-Sub Kwak
Abstract: A semiconductor device includes a transmission circuit coupled between a first voltage supply node and a second voltage supply node, and suitable for outputting an output data signal corresponding to a data value to an output terminal during a data output enable period, and a switching circuit coupled between the first and second voltage supply nodes, and suitable for providing a current path between the first and second voltage supply nodes during a data output disable period.
-
公开(公告)号：US10936409B2
公开(公告)日：2021-03-02
申请号：US16199333
申请日：2018-11-26
Applicant: SK hynix Inc.
Inventor： Kang-Sub Kwak , Ki-Up Kim , Young-Jun Yoon
Abstract: A memory system comprises: a memory cell array suitable for storing first data and a first parity, which is used to correct an error of the first data; and an error correcting circuit suitable for generating second data and a second parity, which includes bits obtained by correcting an error of the first parity and a bit obtained by correcting an error of a second sub-parity; wherein the error correcting circuit includes: a single error correction and double error detection (SECDED) parity generator suitable for generating a second pre-parity, which includes a first sub-parity and the second sub-parity; a syndrome decoder suitable for generating a first parity error flag and a first data error flag by decoding a syndrome; a SEC parity corrector suitable for correcting an error of the first parity based on the first parity error flag; a DED parity error detector suitable for generating a second sub-parity error flag based on an error information of the first data used to generate the second sub-parity; and a DED parity corrector suitable for correcting any error of the second sub-parity based on the second sub-parity error flag.
-
Patent Agency Ranking
公开(公告)号：US09490853B2
公开(公告)日：2016-11-08
申请号：US14856409
申请日：2015-09-16
Inventor： Kang-Sub Kwak , Jong-Hyun Ra , Oh-Kyong Kwon , Hae-Rang Choi , Yong-Ju Kim
Abstract: A data transmitter may include a transmitter circuit and a calibration controller. The transmitter circuit is configured to be coupled to a receiver through a channel, and configured to provide an output signal to the channel based on an input signal and adjust an output impedance value according to a bias signal. The calibration controller is configured to adjust the bias signal by comparing the output signal of the transmitter circuit to a reference signal during a calibration operation.
Abstract translation: 数据发射机可以包括发射机电路和校准控制器。 发射机电路被配置为通过信道耦合到接收机，并且被配置为基于输入信号向信道提供输出信号，并根据偏置信号调整输出阻抗值。 校准控制器被配置为通过在校准操作期间将发射机电路的输出信号与参考信号进行比较来调整偏置信号。
-
公开(公告)号：US11221909B2
公开(公告)日：2022-01-11
申请号：US16802194
申请日：2020-02-26
Applicant: SK hynix Inc.
Inventor： Kang-Sub Kwak , Young-Jun Yoon , Joon-Yong Choi
Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.
-
公开(公告)号：US11216331B2
公开(公告)日：2022-01-04
申请号：US16802168
申请日：2020-02-26
Applicant: SK hynix Inc.
Inventor： Kang-Sub Kwak , Young-Jun Yoon , Joon-Yong Choi
Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.
-
公开(公告)号：US11200111B2
公开(公告)日：2021-12-14
申请号：US16802215
申请日：2020-02-26
Applicant: SK hynix Inc.
Inventor： Kang-Sub Kwak , Young-Jun Yoon , Joon-Yong Choi
Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.
-
公开(公告)号：US10861515B2
公开(公告)日：2020-12-08
申请号：US16128803
申请日：2018-09-12
Applicant: SK hynix Inc.
Inventor： Kang-Sub Kwak , Sang-Sic Yoon , Young-Jun Yoon
Abstract: An operating method for a semiconductor memory device includes: generating a whole-domain-crossing-unit reset signal based on a domain-crossing-unit reset signal input to a whole-domain-crossing-unit-reset-signal generator; and resetting a counter synchronized to a data clock of a domain-crossing unit based on the whole-domain-crossing-unit reset signal during a data clock preparation section in which the data clock does not toggle.
-
-
-
-
-
-
-
-
-
Search Results
11
records
(took 0.015 seconds)
