公开(公告)号：US09305642B2

公开(公告)日：2016-04-05

申请号：US14050069

申请日：2013-10-09

Applicant: SK hynix Inc.

Inventor： Dong Yean Oh ,  Woon Ha Yim ,  Mi Na Kim

IPC: G06F12/00 ,  G11C13/00 ,  H01L27/10

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/71 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/101

Abstract: Resistance memory device and apparatus, a fabrication method thereof, an operation method thereof, and a system including the same are provided. The resistance memory device may include a data storage unit and a first interconnection connected to the data storage unit. A first access device may be connected in series with the data storage unit and a second access device may be connected in series with the first access device. A second interconnection may be connected to the second access device. A third interconnection may be connected to the first access device to drive the first access device and a fourth interconnection connected to the second access device to drive the second access device.

Abstract translation: 提供了电阻记忆装置和装置，其制造方法，其操作方法和包括该电阻记忆装置的装置。 电阻存储器件可以包括数据存储单元和连接到数据存储单元的第一互连。 第一接入设备可以与数据存储单元串联连接，并且第二接入设备可以与第一接入设备串联连接。 第二互连可以连接到第二接入设备。 第三互连可以连接到第一接入设备以驱动第一接入设备和连接到第二接入设备的第四互连来驱动第二接入设备。

公开(公告)号：US11864370B2

公开(公告)日：2024-01-02

申请号：US17737393

申请日：2022-05-05

Applicant: SK hynix Inc.

Inventor： Kang Yoo Song ,  Mi Na Kim

IPC: H10B12/00 ,  H01L21/28 ,  H01L49/02

CPC classification number: H10B12/033 ,  H01L21/28238 ,  H01L28/91 ,  H01L28/92 ,  H10B12/315 ,  H10B12/318

Abstract: Present invention relates to a method of fabricating a semiconductor device that can facilitate the processes of etching a supporter and removing a mold layer. According to the present invention, a method of fabricating a semiconductor device semiconductor device comprises: sequentially forming a substructure over a substrate and a etch stop layer over the substructure; forming a stack structure of alternately stacked mold layers and supporter layers over the etch stop layer; forming a plurality of supporter holes in the stack structure exposing the etch stop layer; forming a sacrificial layer filling each of the plurality of the supporter holes; forming a plurality of lower electrode openings exposing the substructure by etching the sacrificial layer and the stack structure; and forming a lower electrode inside the plurality of lower electrode openings.