UART aggregation and JTAG selection circuitry for a multi-solid state drive environment

    公开(公告)号:US11809355B2

    公开(公告)日:2023-11-07

    申请号:US17169062

    申请日:2021-02-05

    Applicant: SK hynix Inc.

    CPC classification number: G06F13/385 G06F13/387 G06F13/409 H03K19/1737

    Abstract: An adaptor device includes a first interface for coupling to a first processor, a second interface for coupling to a second processor, the second interface being different than the first interface, and a plurality of third interfaces, which are different than either the first interface or the second interface. The plurality of third interfaces are configured for coupling to a corresponding plurality of external devices. The adaptor device is configured to receive, at the first interface, a first signal from the first processor. In response to the first signal, the adaptor device couples through the plurality of third interfaces to the plurality of external devices to enable the first processor substantially concurrent access to the plurality of external devices. The adaptor device is also configured to receive, at the first interface, a second signal from the first processor. In response to the second signal, the adaptor device couples the second processor with a selected one of the plurality of external devices.

    UART AGGREGATION AND JTAG SELECTION CIRCUITRY FOR A MULTI-SOLID STATE DRIVE ENVIRONMENT

    公开(公告)号:US20220253395A1

    公开(公告)日:2022-08-11

    申请号:US17169062

    申请日:2021-02-05

    Applicant: SK hynix Inc.

    Abstract: An adaptor device includes a first interface for coupling to a first processor, a second interface for coupling to a second processor, the second interface being different than the first interface, and a plurality of third interfaces, which are different than either the first interface or the second interface. The plurality of third interfaces are configured for coupling to a corresponding plurality of external devices. The adaptor device is configured to receive, at the first interface, a first signal from the first processor. In response to the first signal, the adaptor device couples through the plurality of third interfaces to the plurality of external devices to enable the first processor substantially concurrent access to the plurality of external devices. The adaptor device is also configured to receive, at the first interface, a second signal from the first processor. In response to the second signal, the adaptor device couples the second processor with a selected one of the plurality of external devices.

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