公开(公告)号：US20140010033A1

公开(公告)日：2014-01-09

申请号：US13711279

申请日：2012-12-11

Applicant: SK HYNIX INC.

Inventor： Sam Kyu WON ,  Sung Hyun JUNG

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C7/22

Abstract: A memory system includes first to third memory devices each having an input terminal for receiving a token signal and an output terminal for transmitting the token signal, wherein the input terminal of each of the first to third memory devices are connected to the output terminal of another memory device through a ring topology, and the first to third memory devices substantially simultaneously perform an operation of consuming a peak current in response to any one of a plurality of token signals.

Abstract translation: 存储器系统包括第一至第三存储器件，每个存储器件具有用于接收令牌信号的输入端子和用于发送令牌信号的输出端子，其中第一至第三存储器件中的每一个的输入端子连接到另一个的输出端子 存储器件，并且第一至第三存储器件基本上同时执行响应于多个令牌信号中的任何一个来消耗峰值电流的操作。

公开(公告)号：US20160293271A1

公开(公告)日：2016-10-06

申请号：US14953194

申请日：2015-11-27

Applicant: SK hynix Inc.

Inventor： Sam Kyu WON ,  Myung Su KIM ,  Jae Won CHA

IPC: G11C29/04 ,  G11C16/34 ,  G11C16/12 ,  G11C16/28

CPC classification number: G11C29/025 ,  G11C16/28 ,  G11C16/3459 ,  G11C16/349 ,  G11C29/12005 ,  G11C29/50004 ,  G11C2029/1202

Abstract: A method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.

Abstract translation: 一种操作半导体存储器件的方法包括至少对多个页面中的每一个施加一个编程脉冲; 通过初始测试电压在多个页面中的参考页面上执行预读操作; 通过控制初始测试电压重复预读操作，直到预读操作的结果通过; 将预读操作的结果作为参考测试电压设置为初始测试电压; 以及通过参考测试电压对多个页面进行读取操作来检测多个页面中的缺陷页面。

公开(公告)号：US20140160864A1

公开(公告)日：2014-06-12

申请号：US13845350

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Sam Kyu WON ,  Cheul Hee KOO ,  Duck Ju KIM ,  Won Kyung KANG

IPC: G11C5/14 ,  G05F3/02

CPC classification number: G11C5/147 ,  G05F3/02 ,  G11C5/145

Abstract: The present technology relates to an electronic device, and more particularly, to a semiconductor device. The semiconductor device includes a peripheral circuit, a power output line connected to the peripheral circuit and configured to transmit an operation voltage to the peripheral circuit, a current compensator including an OP-amplifier connected to the power output line, and a capacitor connected between an output terminal of the OP-amplifier and the power output line.

Abstract translation: 本技术涉及电子设备，更具体地，涉及一种半导体器件。 半导体器件包括外围电路，连接到外围电路并被配置为向外围电路传输工作电压的电力输出线，包括连接到电力输出线的OP放大器的电流补偿器，以及连接在外部电路 OP放大器的输出端和电源输出线。

公开(公告)号：US20180130544A1

公开(公告)日：2018-05-10

申请号：US15866094

申请日：2018-01-09

Applicant: SK hynix Inc.

Inventor： Sam Kyu WON ,  Myung Su KIM ,  Jae Won CHA

IPC: G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  G11C16/28 ,  G11C16/34

CPC classification number: G11C29/025 ,  G11C16/28 ,  G11C16/3459 ,  G11C16/349 ,  G11C29/12005 ,  G11C29/50004 ,  G11C2029/1202

Abstract: A method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.

公开(公告)号：US20140258611A1

公开(公告)日：2014-09-11

申请号：US13934994

申请日：2013-07-03

Applicant: SK Hynix Inc.

Inventor： Sam Kyu WON ,  Duck Ju KIM ,  Won Kyung KANG

IPC: G06F3/06

CPC classification number: G11C16/22 ,  G11C7/02 ,  G11C8/20

Abstract: A semiconductor device includes a memory cell array includes a plurality of memory blocks, each of the memory blocks including a plurality of pages, wherein at least one of the plurality of memory blocks functions as a first storage unit to store a plurality of page addresses associated with the plurality of pages. A second storage unit loads a page address stored in the first storage unit. A control circuit is configured to cancel a program operation if an externally inputted page address is less than or equal to the page address loaded into the second storage unit, and perform the program operation and update the second storage unit with the externally inputted page address if the externally input page address is greater than the page address loaded into the second storage unit.

Abstract translation: 半导体器件包括存储单元阵列，其包括多个存储器块，每个存储器块包括多个存储器块，其中所述多个存储器块中的至少一个用作第一存储单元，用于存储多个页面地址相关联 与多页。 第二存储单元加载存储在第一存储单元中的页地址。 如果外部输入的页面地址小于或等于加载到第二存储单元中的页面地址，则控制电路被配置为取消编程操作，并且执行程序操作并且用外部输入的页面地址来更新第二存储单元，如果 外部输入的页面地址大于加载到第二个存储单元中的页面地址。