公开(公告)号：US20140003159A1

公开(公告)日：2014-01-02

申请号：US13709337

申请日：2012-12-10

Applicant: SK HYNIX INC.

Inventor： Sung Hyun JUNG

IPC: G11C16/04

CPC classification number: G11C16/04 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/30

Abstract: A nonvolatile memory device including a plurality of memory cells arranged at a region where word lines and bit lines cross each other, a control logic configured to control an erase operation for the memory cells, and a voltage generator configured to apply an erase voltage to the memory cells according to control of the control logic, and collect the applied erase voltage to reuse.

Abstract translation: 一种非易失性存储器件，包括布置在字线和位线彼此交叉的区域的多个存储器单元，配置为控制对存储单元的擦除操作的控制逻辑，以及被配置为向擦除电压施加擦除电压的电压发生器 存储单元根据控制逻辑的控制，并收集施加的擦除电压以重新使用。

公开(公告)号：US20150117129A1

公开(公告)日：2015-04-30

申请号：US14219838

申请日：2014-03-19

Applicant: SK hynix Inc.

Inventor： Sung Hyun JUNG

IPC: G11C7/00

CPC classification number: G11C16/107 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit suitable for generating program and erase voltages and applying the program and erase voltages to the plurality of memory cells when program and erase operations are performed on the plurality of memory cells, and a control logic suitable for controlling the peripheral circuit unit during the program and erase operations and counting a pulse number of the program and erase voltages to store a resultant count number as status data.

Abstract translation: 半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储器单元，外围电路适用于产生编程和擦除电压，并且在对多个存储单元执行编程和擦除操作时将编程和擦除电压施加到多个存储器单元 存储单元和适于在编程和擦除操作期间控制外围电路单元的控制逻辑，并且对程序的脉冲数进行计数和擦除电压以存储合成计数作为状态数据。

公开(公告)号：US20140010033A1

公开(公告)日：2014-01-09

申请号：US13711279

申请日：2012-12-11

Applicant: SK HYNIX INC.

Inventor： Sam Kyu WON ,  Sung Hyun JUNG

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C7/22

Abstract: A memory system includes first to third memory devices each having an input terminal for receiving a token signal and an output terminal for transmitting the token signal, wherein the input terminal of each of the first to third memory devices are connected to the output terminal of another memory device through a ring topology, and the first to third memory devices substantially simultaneously perform an operation of consuming a peak current in response to any one of a plurality of token signals.

Abstract translation: 存储器系统包括第一至第三存储器件，每个存储器件具有用于接收令牌信号的输入端子和用于发送令牌信号的输出端子，其中第一至第三存储器件中的每一个的输入端子连接到另一个的输出端子 存储器件，并且第一至第三存储器件基本上同时执行响应于多个令牌信号中的任何一个来消耗峰值电流的操作。

公开(公告)号：US20140003167A1

公开(公告)日：2014-01-02

申请号：US13710895

申请日：2012-12-11

Applicant: SK HYNIX INC.

Inventor： Sung Hyun JUNG

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C7/1006 ,  G11C16/00 ,  G11C16/349 ,  G11C29/52 ,  G11C2029/0409

Abstract: A nonvolatile memory device including a plurality of memory cells arranged at a region where word lines and bit lines cross each other; a plurality of data read/write circuits divided into a plurality of groups, and configured to store data in the memory cells or read data stored in the memory cells, according to an operation mode; a pass/fail check unit configured to determine a pass/fail of an operation for each of the data read/write circuit groups; and a current sensing check unit configured to selectively perform a fail bit count operation on the data read/write circuit groups, according to a determination result of the pass/fail check unit.

Abstract translation: 一种非易失性存储器件，包括布置在字线和位线彼此交叉的区域的多个存储单元; 多个数据读/写电路，被分成多个组，并且被配置为根据操作模式将数据存储在存储单元中或读取存储在存储单元中的数据; 通过/失败检查单元，被配置为确定每个数据读/写电路组的操作的通过/失败; 以及电流检测单元，被配置为根据通过/失败检查单元的确定结果选择性地对数据读/写电路组执行故障位计数操作。