公开(公告)号：US20140258611A1

公开(公告)日：2014-09-11

申请号：US13934994

申请日：2013-07-03

Applicant: SK Hynix Inc.

Inventor： Sam Kyu WON ,  Duck Ju KIM ,  Won Kyung KANG

IPC: G06F3/06

CPC classification number: G11C16/22 ,  G11C7/02 ,  G11C8/20

Abstract: A semiconductor device includes a memory cell array includes a plurality of memory blocks, each of the memory blocks including a plurality of pages, wherein at least one of the plurality of memory blocks functions as a first storage unit to store a plurality of page addresses associated with the plurality of pages. A second storage unit loads a page address stored in the first storage unit. A control circuit is configured to cancel a program operation if an externally inputted page address is less than or equal to the page address loaded into the second storage unit, and perform the program operation and update the second storage unit with the externally inputted page address if the externally input page address is greater than the page address loaded into the second storage unit.

Abstract translation: 半导体器件包括存储单元阵列，其包括多个存储器块，每个存储器块包括多个存储器块，其中所述多个存储器块中的至少一个用作第一存储单元，用于存储多个页面地址相关联 与多页。 第二存储单元加载存储在第一存储单元中的页地址。 如果外部输入的页面地址小于或等于加载到第二存储单元中的页面地址，则控制电路被配置为取消编程操作，并且执行程序操作并且用外部输入的页面地址来更新第二存储单元，如果 外部输入的页面地址大于加载到第二个存储单元中的页面地址。

公开(公告)号：US20240379137A1

公开(公告)日：2024-11-14

申请号：US18475028

申请日：2023-09-26

Applicant: SK hynix Inc.

Inventor： Won Jae CHOI ,  Duck Ju KIM

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  H03K19/20

Abstract: A page buffer may include a bit line connection circuit configured to connect or disconnect a bit line and a first node, a plurality of latch circuits that is connected to the first node in common. The page buffer may further include, and logical operation circuit configured to perform a logical operation by using one or more of a voltage level of the first node and a voltage level of a second node as an input and to set the voltage level of the first node responsive to results of the operational operation.

公开(公告)号：US20160086669A1

公开(公告)日：2016-03-24

申请号：US14587151

申请日：2014-12-31

Applicant: SK hynix Inc.

Inventor： Nam Kyeong KIM ,  Duck Ju KIM

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C5/063 ,  G11C16/08 ,  G11C16/30 ,  G11C16/3427

Abstract: A nonvolatile memory device includes a block switching unit which transmits an operation signal to a memory cell array, and a voltage sustaining block which provides a voltage to sustain the operation signal to an arbitrary interconnection overlapping the block switching unit.

Abstract translation: 非易失性存储器件包括：将操作信号发送到存储单元阵列的块切换单元;以及向与块切换单元重叠的任意互连提供维持运算信号的电压的电压维持块。

公开(公告)号：US20140160864A1

公开(公告)日：2014-06-12

申请号：US13845350

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Sam Kyu WON ,  Cheul Hee KOO ,  Duck Ju KIM ,  Won Kyung KANG

IPC: G11C5/14 ,  G05F3/02

CPC classification number: G11C5/147 ,  G05F3/02 ,  G11C5/145

Abstract: The present technology relates to an electronic device, and more particularly, to a semiconductor device. The semiconductor device includes a peripheral circuit, a power output line connected to the peripheral circuit and configured to transmit an operation voltage to the peripheral circuit, a current compensator including an OP-amplifier connected to the power output line, and a capacitor connected between an output terminal of the OP-amplifier and the power output line.

Abstract translation: 本技术涉及电子设备，更具体地，涉及一种半导体器件。 半导体器件包括外围电路，连接到外围电路并被配置为向外围电路传输工作电压的电力输出线，包括连接到电力输出线的OP放大器的电流补偿器，以及连接在外部电路 OP放大器的输出端和电源输出线。

公开(公告)号：US20140010026A1

公开(公告)日：2014-01-09

申请号：US13711448

申请日：2012-12-11

Applicant: SK HYNIX INC.

Inventor： Byung Ryul KIM ,  Cheul Hee KOO ,  Duck Ju KIM

IPC: G11C7/00

CPC classification number: G11C5/147 ,  G11C7/00 ,  G11C8/08 ,  G11C11/56 ,  G11C11/5628 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0092

Abstract: A nonvolatile memory device including a plurality of memory cells arranged at a region where a word line and a bit line cross each other, a voltage generator configured to generate a program voltage to apply to the word line by increasing the program voltage by an increment whenever a program loop is repeated, a current sensing check unit configured to compare a number of failed memory cells among the memory cells to first and second reference values, and a control logic configured to control the voltage generator to change the increment according to the comparison result of the current sensing check unit.

Abstract translation: 一种非易失性存储器件，包括布置在字线和位线彼此交叉的区域的多个存储单元，电压发生器被配置为通过增加编程电压来产生程序电压以施加到字线 重复程序循环，电流感测检查单元，被配置为将存储器单元中的多个故障存储器单元与第一和第二参考值进行比较;以及控制逻辑，被配置为根据比较结果控制电压发生器改变增量 的电流检测单元。