公开(公告)号：US20150169235A1

公开(公告)日：2015-06-18

申请号：US14200312

申请日：2014-03-07

Applicant: SK hynix Inc.

Inventor： Won Kyung KANG

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0634 ,  G06F3/0679 ,  G06F3/0688 ,  G06F13/1694 ,  Y02D10/14

Abstract: A data storage device includes a memory device and a controller suitable for controlling an operation of the memory device according to a memory interface mode between the memory device and the controller. The controller performs a memory interface matching operation when there is a mismatch between the memory interface modes of the memory device and the controller.

Abstract translation: 数据存储装置包括存储装置和适于根据存储装置与控制器之间的存储器接口模式来控制存储装置的操作的控制器。 当存储器件的存储器接口模式与控制器之间存在不匹配时，控制器执行存储器接口匹配操作。

公开(公告)号：US20150113355A1

公开(公告)日：2015-04-23

申请号：US14156215

申请日：2014-01-15

Applicant: SK hynix Inc.

Inventor： Won Kyung KANG

IPC: G06F11/10

CPC classification number: G06F11/1048

Abstract: A data storage device includes a nonvolatile memory device, an error correction code unit suitable for detecting and correcting a data error read from the nonvolatile memory device in response to an operation clock, and a clock unit suitable for selectively providing the operation clock to the error correction code unit depending on whether the data is read from the nonvolatile memory device or not.

Abstract translation: 数据存储装置包括非易失性存储装置，适用于响应于操作时钟检测和校正从非易失性存储装置读取的数据错误的纠错码单元，以及适于选择性地向错误提供操作时钟的时钟单元 取决于是否从非易失性存储器件读取数据的校正码单元。

公开(公告)号：US20140258611A1

公开(公告)日：2014-09-11

申请号：US13934994

申请日：2013-07-03

Applicant: SK Hynix Inc.

Inventor： Sam Kyu WON ,  Duck Ju KIM ,  Won Kyung KANG

IPC: G06F3/06

CPC classification number: G11C16/22 ,  G11C7/02 ,  G11C8/20

Abstract: A semiconductor device includes a memory cell array includes a plurality of memory blocks, each of the memory blocks including a plurality of pages, wherein at least one of the plurality of memory blocks functions as a first storage unit to store a plurality of page addresses associated with the plurality of pages. A second storage unit loads a page address stored in the first storage unit. A control circuit is configured to cancel a program operation if an externally inputted page address is less than or equal to the page address loaded into the second storage unit, and perform the program operation and update the second storage unit with the externally inputted page address if the externally input page address is greater than the page address loaded into the second storage unit.

Abstract translation: 半导体器件包括存储单元阵列，其包括多个存储器块，每个存储器块包括多个存储器块，其中所述多个存储器块中的至少一个用作第一存储单元，用于存储多个页面地址相关联 与多页。 第二存储单元加载存储在第一存储单元中的页地址。 如果外部输入的页面地址小于或等于加载到第二存储单元中的页面地址，则控制电路被配置为取消编程操作，并且执行程序操作并且用外部输入的页面地址来更新第二存储单元，如果 外部输入的页面地址大于加载到第二个存储单元中的页面地址。

公开(公告)号：US20220309003A1

公开(公告)日：2022-09-29

申请号：US17467062

申请日：2021-09-03

Applicant: SK hynix Inc.

Inventor： Won Kyung KANG

IPC: G06F12/0888 ,  G06F12/0873 ,  G06F12/0891 ,  G06F12/02 ,  G06K9/62 ,  G06N3/08

Abstract: A memory controller includes: a map cache area for storing a map cache lines including mapping information between a logical address and a physical address; a victim map cache line selector for selecting a victim map cache line among the map cache lines, using a victim map cache line selection model trained by using a storage state information as training data, when a physical address corresponding to a logical address of an operation request is absent in the map cache area; and a map data controller for removing the selected victim map cache line from the map cache area, providing the removed victim map cache line to a memory device, receiving a target map cache line including the physical address corresponding to the logical address of the operation request from the memory device, and storing the target map cache line in the map cache area.

公开(公告)号：US20150052374A1

公开(公告)日：2015-02-19

申请号：US14093321

申请日：2013-11-29

Applicant: SK hynix Inc.

Inventor： Won Kyung KANG

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3275 ,  G06F1/3278 ,  Y02D10/14 ,  Y02D10/157 ,  Y02D10/171 ,  Y02D50/20

Abstract: A data processing system includes a host device; and a data storage device including an interface unit which is configured to interface with the host device, and configured to store data provided from the host device or provide data to the host device, in response to a request from the host device, wherein the data storage device is configured to interrupt power supply to the interface unit while the host device operates in a power saving mode.

Abstract translation: 数据处理系统包括主机设备; 以及数据存储装置，其包括接口单元，其被配置为与所述主机设备接口，并且被配置为存储从所述主机设备提供的数据或者向所述主机设备提供数据，响应于来自所述主机设备的请求，其中所述数据 存储设备被配置为在主机设备以省电模式操作时中断对接口单元的电源。

公开(公告)号：US20140160864A1

公开(公告)日：2014-06-12

申请号：US13845350

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Sam Kyu WON ,  Cheul Hee KOO ,  Duck Ju KIM ,  Won Kyung KANG

IPC: G11C5/14 ,  G05F3/02

CPC classification number: G11C5/147 ,  G05F3/02 ,  G11C5/145

Abstract: The present technology relates to an electronic device, and more particularly, to a semiconductor device. The semiconductor device includes a peripheral circuit, a power output line connected to the peripheral circuit and configured to transmit an operation voltage to the peripheral circuit, a current compensator including an OP-amplifier connected to the power output line, and a capacitor connected between an output terminal of the OP-amplifier and the power output line.

Abstract translation: 本技术涉及电子设备，更具体地，涉及一种半导体器件。 半导体器件包括外围电路，连接到外围电路并被配置为向外围电路传输工作电压的电力输出线，包括连接到电力输出线的OP放大器的电流补偿器，以及连接在外部电路 OP放大器的输出端和电源输出线。

公开(公告)号：US20140126285A1

公开(公告)日：2014-05-08

申请号：US13846599

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Won Kyung KANG

IPC: G11C16/26 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/349 ,  G11C2216/14

Abstract: A semiconductor memory device and an operating method of the semiconductor memory device change a read voltage used in a read operation by performing a moving read operation, a randomize operation, and a program/erase compensation operation independently or in combination, thereby stably performing the read operation without an error and reducing a time for the read operation even when distribution of threshold voltages of the memory cells is changed according to a program/erase cycling effect or a retention effect.

Abstract translation: 半导体存储器件和半导体存储器件的操作方法通过独立地或组合地执行移动读取操作，随机化操作和编程/擦除补偿操作来改变读取操作中使用的读取电压，从而稳定地执行读取 即使在存储单元的阈值电压的分配根据编程/擦除循环效应或保留效果而改变时，也不会出现错误的操作并且减少读取操作的时间。