公开(公告)号：US20220189534A1

公开(公告)日：2022-06-16

申请号：US17521331

申请日：2021-11-08

Applicant: SK hynix Inc.

Inventor： Jeong Jin HWANG ,  Sung Nyou YU ,  Duck Hwa HONG ,  Sang Ah HYUN ,  Soo Hwan KIM

IPC: G11C11/406 ,  G11C11/408

Abstract: An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.

公开(公告)号：US20190056956A1

公开(公告)日：2019-02-21

申请号：US15949842

申请日：2018-04-10

Applicant: SK hynix Inc.

Inventor： Chul Moon JUNG ,  Joo Hyeon LEE ,  Sung Nyou YU

IPC: G06F9/4401 ,  H03K5/156 ,  H03K21/38 ,  G11C17/16 ,  G11C17/18

Abstract: A semiconductor device may include a fuse array configured to output fuse data. The semiconductor device may include a latch circuit configured to store the fuse data during an enabled section of a dummy boot-up signal, output the stored fuse data as a fuse data information signal during a disabled section of the dummy boot-up signal, and fix the fuse data information signal to a specific level during the enabled section of the dummy boot-up signal regardless of the stored fuse data.

公开(公告)号：US20240112718A1

公开(公告)日：2024-04-04

申请号：US18535647

申请日：2023-12-11

Applicant: SK hynix Inc.

Inventor： Jeong Jin HWANG ,  Sung Nyou YU ,  Duck Hwa HONG ,  Sang Ah HYUN ,  Soo Hwan KIM

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C11/40603 ,  G11C11/4085 ,  G11C11/406 ,  G11C11/40618

Abstract: An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.

公开(公告)号：US20230223061A1

公开(公告)日：2023-07-13

申请号：US17741099

申请日：2022-05-10

Applicant: SK hynix Inc.

Inventor： Jeong Jin HWANG ,  Sung Nyou YU ,  Min Jun CHOI

IPC: G11C8/08 ,  G11C8/10

CPC classification number: G11C8/08 ,  G11C8/10

Abstract: A semiconductor device includes an address input circuit configured to boost a voltage level of at least one bit of a row address to generate a boosting address and to drive a signal of a first node based on other bits of the row address and the boosting address. The semiconductor device also includes a word line selection signal generation circuit configured to drive a signal of a second node based on the signal of the first node and to generate a word line selection signal for selecting a word line based on the signal of the second node.