公开(公告)号：US20220406367A1

公开(公告)日：2022-12-22

申请号：US17480832

申请日：2021-09-21

Applicant: SK hynix Inc.

Inventor： Hyun Seung KIM ,  Ho Uk SONG ,  Tae Kyun SHIN ,  Min Jun CHOI ,  Duck Hwa HONG

IPC: G11C11/406 ,  G11C11/4076

Abstract: An electronic device includes an intelligent refresh control circuit generating an intelligent refresh pulse with a pulse that has a generation period that is adjusted based on the number of generations of an auto refresh signal during an intelligent refresh operation, and an internal refresh signal generation circuit outputting one of a self-refresh pulse including a pulse that is periodically generated by an enable signal during a self-refresh operation and the intelligent refresh pulse as an internal refresh signal.

公开(公告)号：US20230223061A1

公开(公告)日：2023-07-13

申请号：US17741099

申请日：2022-05-10

Applicant: SK hynix Inc.

Inventor： Jeong Jin HWANG ,  Sung Nyou YU ,  Min Jun CHOI

IPC: G11C8/08 ,  G11C8/10

CPC classification number: G11C8/08 ,  G11C8/10

Abstract: A semiconductor device includes an address input circuit configured to boost a voltage level of at least one bit of a row address to generate a boosting address and to drive a signal of a first node based on other bits of the row address and the boosting address. The semiconductor device also includes a word line selection signal generation circuit configured to drive a signal of a second node based on the signal of the first node and to generate a word line selection signal for selecting a word line based on the signal of the second node.

公开(公告)号：US20170117023A1

公开(公告)日：2017-04-27

申请号：US15017994

申请日：2016-02-08

Applicant: SK hynix Inc.

Inventor： Min Soo PARK ,  Jin Se KIM ,  Moon Yub NA ,  Min Jun CHOI ,  Hyun Wook HAN

IPC: G11C7/10 ,  G11C8/10 ,  G11C7/12 ,  G11C7/06

CPC classification number: G11C7/1084 ,  G11C7/02 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1057 ,  G11C8/10 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/36 ,  G11C29/44 ,  G11C29/56008 ,  G11C29/56012 ,  G11C2029/1208 ,  G11C2029/4402

Abstract: A semiconductor system may include a first semiconductor device configured to output commands, addresses and data. The semiconductor system may include a second semiconductor device configured to convert a logic level combination of the data when only any one of bits of the data is a different logic level, and store the data in response to the commands and the addresses, in a write operation.