公开(公告)号：US10740179B2

公开(公告)日：2020-08-11

申请号：US16182928

申请日：2018-11-07

申请人： SK hynix Inc.

发明人： Sungeun Lee

IPC分类号： G06F11/00 ,  G06F11/10 ,  H03M13/29 ,  G11C29/52 ,  G11C29/00 ,  G11C29/04

摘要： An error correction method and a chip kill detection method of a memory including a plurality of chips may be provided. The method may include a first data error detection step of detecting whether an error exists in data outputted from the plurality of chips. The method may include a random error correction step of correcting an error occurred in data when it is detected in the first data error detection step that an error exists. The method may include a chip kill detection step of determining, when an error occurs even after the random error correction step, that a chip kill error has occurred, and detecting a chip where the chip kill error has occurred, by correcting the error through assuming one chip among the plurality of chips as a chip where the chip kill error has occurred.

公开(公告)号：US10261860B2

公开(公告)日：2019-04-16

申请号：US15611151

申请日：2017-06-01

申请人： SK hynix Inc.

发明人： Sungeun Lee ,  Jung Hyun Kwon ,  Yong Ju Kim ,  Jae Sun Lee ,  Jingzhe Xu

IPC分类号： G11C29/00 ,  G06F11/10 ,  H03M13/19 ,  H03M13/15 ,  G11C29/52 ,  G11C29/04

摘要： A semiconductor system includes a host and a media controller. The host may generate first host parities from first host data based on an error check matrix. The media controller may include a first input/output (I/O) circuit and a second I/O circuit. The media controller may generate first media data and first media parities based on the first host data and the first host parities. The first I/O circuit may generate, based on the error check matrix, first internal data by correcting errors in the first host data using the first host parities. The second I/O circuit may generate the first media data and the first media parities from the first internal data.

公开(公告)号：US10108250B2

公开(公告)日：2018-10-23

申请号：US15230734

申请日：2016-08-08

申请人： SK hynix Inc.

发明人： Yong Ju Kim ,  Jung Hyun Kwon ,  Donggun Kim ,  Sungeun Lee ,  Jae Sun Lee ,  Sang Gu Jo ,  Jingzhe Xu ,  Do Sun Hong

IPC分类号： G06F1/32 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/121 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/406

摘要： In an embodiment of the present disclosure, a memory module may be provided. In an embodiment of the present disclosure, a system may be provided. In an embodiment of the present disclosure, an operation of a system and memory module may be provided. The memory module may include a plurality of ranks in which a defragmentation operation of a memory is performed based on entrance of a low-power operation mode, and a vacant region of the memory is powered off based on entrance of a self-refresh mode after the defragmentation operation is ended. The memory module may include a page table of which data are updated based on an ending of the defragmentation operation of the memory.

公开(公告)号：US10114561B2

公开(公告)日：2018-10-30

申请号：US15493289

申请日：2017-04-21

申请人： SK hynix Inc.

发明人： Do-Sun Hong ,  Jung Hyun Kwon ,  Donggun Kim ,  Yong Ju Kim ,  Sungeun Lee ,  Jae Sun Lee ,  Sang Gu Jo ,  Jingzhe Xu

IPC分类号： G11C13/00 ,  G06F3/06 ,  G11C16/34 ,  G06F12/10 ,  G06F12/02

摘要： A memory controller may be provided. The memory controller may include a wear-leveler may be configured to determine whether execution of a swapping operation is required based on reception of a write command for a stack region.

公开(公告)号：US10083103B1

公开(公告)日：2018-09-25

申请号：US15823190

申请日：2017-11-27

申请人： SK hynix Inc.

发明人： Jung Hyun Kwon ,  Sungeun Lee ,  Sang Gu Jo

IPC分类号： G11C7/00 ,  G06F11/30 ,  H01L27/24 ,  G06F1/32 ,  G11C13/00 ,  H01L45/00 ,  G11C7/10

摘要： A circuit for calculating power consumption of a phase change memory (PCM) device may be provided. The circuit may include a plurality of pipelines and an arithmetic logic circuit. The plurality of pipelines may be configured to correspond to a plurality of write periods exhibiting different power consumption values during a write operation of the PCM device executed by a write command. The plurality of pipelines may shift or transmit data in synchronization with a clock signal. The arithmetic logic circuit may be configured to perform an adding operation of all of deviations of the power consumption values at a point of time that data transmission between at least two of the plurality of pipelines occurs, to thus generate a total power consumption value.