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    Test apparatus
    1.
    发明授权
    Test apparatus 有权

    公开(公告)号：US10983164B2

    公开(公告)日：2021-04-20

    申请号：US16733035

    申请日：2020-01-02

    Applicant: SK hynix Inc. ,  KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION

    Inventor： Chul Woo Kim ,  Dong Yoon Kim ,  In Hwa Jung ,  Yong Ju Kim

    IPC: G01R31/319 ,  G06F11/22 ,  G01R31/28 ,  G01R31/3167

    Abstract: A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers, and provides the second timing information corresponding to the timing differences to the transceivers.

    Memory system including a delegate page and method of identifying a status of a memory system
    2.
    发明授权
    Memory system including a delegate page and method of identifying a status of a memory system 有权

    公开(公告)号：US10475522B2

    公开(公告)日：2019-11-12

    申请号：US15821155

    申请日：2017-11-22

    Applicant: SK hynix Inc.

    Inventor： Donggun Kim ,  Yong Ju Kim ,  Do Sun Hong

    IPC: G11C29/00 ,  G11C29/38 ,  G06F3/06 ,  G11C29/36

    Abstract: A nonvolatile memory system may include a nonvolatile memory device, a delegate page attacker, and a health status analyzer. The nonvolatile memory device may include at least one memory block including a plurality of storage pages and a delegate page. The delegate page attacker may be configured to attack a bit of the delegate page at the same corresponding location as a bit of the storage page in which an error occurs. The health status analyzer may be configured to perform write and read operations for the delegate page and analyzes error information occurred in the write and read operations to determine whether the nonvolatile memory device is in a failure status.

    Memory apparatus and method of wear-leveling of a memory apparatus
    3.
    发明授权
    Memory apparatus and method of wear-leveling of a memory apparatus 有权

    公开(公告)号：US10223255B2

    公开(公告)日：2019-03-05

    申请号：US15821291

    申请日：2017-11-22

    Applicant: SK hynix Inc.

    Inventor： Donggun Kim ,  Yong Ju Kim ,  Do Sun Hong

    IPC: G11C16/04 ,  G06F12/02

    Abstract: A memory apparatus and a method of wear-leveling of a memory apparatus may be provided. The memory apparatus may include a memory having a plurality of storage blocks and a plurality of free blocks. The memory apparatus may include a memory controller configured for performing a first global wear-leveling to move data of a first storage block, which is a hot block among the storage blocks, to a first free block among the free blocks. The memory apparatus may include a memory controller configured for remapping a result of a logic operation of a logical page address of each of the pages in the first storage block and a first security refresh key to a physical page address of each of the pages in the first free block.

    MEMORY APPARATUS AND METHOD OF WEAR-LEVELING OF A MEMORY APPARATUS
    4.
    发明申请
    MEMORY APPARATUS AND METHOD OF WEAR-LEVELING OF A MEMORY APPARATUS 审中-公开

    公开(公告)号：US20180260321A1

    公开(公告)日：2018-09-13

    申请号：US15821291

    申请日：2017-11-22

    Applicant: SK hynix Inc.

    Inventor： Donggun Kim ,  Yong Ju Kim ,  Do Sun Hong

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F12/1466 ,  G06F2212/1052 ,  G06F2212/7201 ,  G06F2212/7211

    Abstract: A memory apparatus and a method of wear-leveling of a memory apparatus may be provided. The memory apparatus may include a memory having a plurality of storage blocks and a plurality of free blocks. The memory apparatus may include a memory controller configured for performing a first global wear-leveling to move data of a first storage block, which is a hot block among the storage blocks, to a first free block among the free blocks. The memory apparatus may include a memory controller configured for remapping a result of a logic operation of a logical page address of each of the pages in the first storage block and a first security refresh key to a physical page address of each of the pages in the first free block.

    System and method for repairing memory
    6.
    发明授权
    System and method for repairing memory 有权

    公开(公告)号：US11538550B2

    公开(公告)日：2022-12-27

    申请号：US16913664

    申请日：2020-06-26

    Applicant: SK hynix Inc.

    Inventor： Hyun Seok Kim ,  Yong Ju Kim ,  Su Hae Woo

    IPC: G06F11/10 ,  G11C29/00 ,  G06F12/02 ,  G06F11/08 ,  G06F11/14

    Abstract: A memory system includes a memory medium and a memory controller. The memory medium has a second address system that is different from a first address system of a host. The memory controller performs a control operation to access the memory medium based on a command from the host. The memory controller is configured to store a second address, corresponding to an address of a read data, when an error of the read data that is outputted from the memory medium is uncorrectable and is configured to repair a region of the memory medium, designated by the second address, when the region of the memory medium that is designated by the second address is repairable.

    All digital phase locked loop
    10.
    发明授权
    All digital phase locked loop 有权

    公开(公告)号：US10038451B2

    公开(公告)日：2018-07-31

    申请号：US15795703

    申请日：2017-10-27

    Applicant: SK hynix Inc. ,  POSTECH ACADEMY-INDUSTRY FOUNDATION

    Inventor： Jae Yoon Sim ,  Min Seob Lee ,  In Hwa Jung ,  Yong Ju Kim

    IPC: H03L7/099 ,  H03L7/07

    CPC classification number: H03L7/0992 ,  H03L7/07 ,  H03L7/081 ,  H03L7/085 ,  H03L2207/50

    Abstract: An all digital phase locked loop (ADPLL) includes an integer part phase processing circuit that outputs an integer part frequency signal using a first value and a second value. The first value is obtained by counting edges of one of a plurality of output clock signals. The second value indicates current edge position information on an edge position of an external reference clock signal with respect to the plurality of output clock signals. The ADPLL further includes a fraction part phase processing circuit that selects two adjacent output clock signals of the plurality of output clock signals according to a prediction selection signal and that generates a fraction part frequency signal using the fraction part phase signal, the prediction selection signal being generated according to a fraction part phase signal indicating fraction part phase information and a signal indicating the current edge position information.

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