公开(公告)号：US20240047003A1

公开(公告)日：2024-02-08

申请号：US18096279

申请日：2023-01-12

Applicant: SK hynix Inc.

Inventor： Seong Ju LEE ,  Yong Sun KIM

IPC: G11C29/10 ,  H01L25/065 ,  G11C7/22

CPC classification number: G11C29/10 ,  H01L25/0657 ,  G11C7/222 ,  H01L2225/06562 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2224/06177 ,  H01L24/06

Abstract: A semiconductor package includes a first memory device configured to output master data after the start of a training operation, and a second memory device configured to sample internal data based on the master data after the start of the training operation, configured to store test codes that adjust a time point at which the internal data are output when a time point at which the master data are output and the time point at which the internal data are output become identical with each other, and configured to program the stored test codes when the training operation is terminated.

公开(公告)号：US20230178171A1

公开(公告)日：2023-06-08

申请号：US17673286

申请日：2022-02-16

Applicant: SK hynix Inc.

Inventor： Yong Sun KIM ,  Mi Hyun HWANG

IPC: G11C29/54

CPC classification number: G11C29/54

Abstract: A memory device includes a fail test circuit configured to generate a fail flag indicating whether a failure was detected in a column line, on the basis of internal data outputted from the column line selected according to a column address, when performing a test, and control the fail flag to indicate that the failure was detected in the column line, on the basis of a fail control signal. The memory device also includes a repair information generation circuit configured to generate, from the column address, a repair column address for repairing the column line, on the basis of the fail flag.

公开(公告)号：US20180090221A1

公开(公告)日：2018-03-29

申请号：US15434990

申请日：2017-02-16

Applicant: SK hynix Inc.

Inventor： Yong Sun KIM ,  Tae Kyun SHIN

IPC: G11C17/18 ,  G11C17/16 ,  G11C29/12

CPC classification number: G11C17/18 ,  G11C7/20 ,  G11C17/16 ,  G11C29/027 ,  G11C29/12 ,  G11C29/24 ,  G11C29/781

Abstract: A boot-up control circuit may be provided. The boot-up control circuit may include a fuse array including a one or more normal fuses and one or more dummy fuses. The boot-up control circuit may include a fuse array controller configured to determine whether or not to start a normal boot-up operation for the one or more normal fuses according to a comparison result between expected data and test fuse data output from the one or more dummy fuses through a test boot-up operation.