公开(公告)号：US20170085260A1

公开(公告)日：2017-03-23

申请号：US15041554

申请日：2016-02-11

Applicant: SK hynix Inc.

Inventor： Tae Kyun SHIN

IPC: H03K17/22 ,  H03K3/037

CPC classification number: H03K17/22 ,  G06F1/24 ,  G06F2211/1097

Abstract: A semiconductor device includes a boot-up start signal generation unit configured to generate a boot-up start signal which is enabled in synchronization with a time at which a preset delay period has passed from a time point at which an initialization signal is enabled after a power-up period is ended, and a boot-up period signal generation unit configured to generate a boot-up period signal which is enabled according to a set pulse generated in synchronization with a time point at which the boot-up start signal is enabled.

公开(公告)号：US20140369150A1

公开(公告)日：2014-12-18

申请号：US14084149

申请日：2013-11-19

Applicant: SK hynix Inc.

Inventor： Tae Kyun SHIN

IPC: G11C8/10

CPC classification number: G11C8/10

Abstract: Column decoders are provided. The column decoder includes a power supplier and a column selection signal generator. The power supplier generates a supply voltage signal from a power voltage in response to a control signal enabled from a start point of time of a write mode or a read mode till an end point of time of a burst length. A level of the supply voltage signal is controlled according to the control signal. The column selection signal generator operates while the supply voltage signal is supplied. The column selection signal generator generates one of column selection signals, which is selectively enabled according to a logic combination of a high-order address signal, a mid-order address signal and a low-order address signal which are generated by decoding column address signals.

Abstract translation: 提供列解码器。 列解码器包括电源和列选择信号发生器。 供电器响应于从写入模式或读取模式的起始点到突发长度的结束时刻使能的控制信号，从电源电压产生电源电压信号。 根据控制信号控制电源电压信号的电平。 列选择信号发生器在提供电源电压信号的同时运行。 列选择信号发生器产生列选择信号之一，根据高位地址信号，中间地址信号和低位地址信号的逻辑组合，这些列选择信号被选择性地使能，该地址信号是通过解码列地址信号 。

公开(公告)号：US20170317671A1

公开(公告)日：2017-11-02

申请号：US15651127

申请日：2017-07-17

Applicant: SK hynix Inc.

Inventor： Tae Kyun SHIN

IPC: H03K17/22 ,  G06F1/24

CPC classification number: H03K17/22 ,  G06F1/24 ,  G06F2211/1097

Abstract: A semiconductor device includes a boot-up start signal generation unit configured to generate a boot-up start signal which is enabled in synchronization with a time at which a preset delay period has passed from a time point at which an initialization signal is enabled after a power-up period is ended, and a boot-up period signal generation unit configured to generate a boot-up period signal which is enabled according to a set pulse generated in synchronization with a time point at which the boot-up start signal is enabled.

公开(公告)号：US20150221395A1

公开(公告)日：2015-08-06

申请号：US14174779

申请日：2014-02-06

Applicant: SK hynix Inc.

Inventor： Tae Kyun SHIN

IPC: G11C17/18 ,  G11C29/04 ,  G11C29/00 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C17/16 ,  G11C29/4401 ,  G11C29/78 ,  G11C2029/4402

Abstract: The semiconductor device includes a latch pulse generator and a data latch unit. The latch pulse generator generates a test section signal in response to a test pulse signal. Further, the latch pulse generator generates a first latch pulse signal in response to the test pulse signal and the test section signal. The data latch unit latches a selection data in response to the first latch pulse signal to generate a fuse data for programming a fuse array.

Abstract translation: 半导体器件包括锁存脉冲发生器和数据锁存单元。 锁存脉冲发生器响应于测试脉冲信号产生测试部分信号。 此外，锁存脉冲发生器响应于测试脉冲信号和测试部分信号产生第一锁存脉冲信号。 数据锁存单元响应于第一锁存脉冲信号而锁存选择数据，以生成用于编程熔丝阵列的熔丝数据。

公开(公告)号：US20150221394A1

公开(公告)日：2015-08-06

申请号：US14174744

申请日：2014-02-06

Applicant: SK hynix Inc.

Inventor： Tae Kyun SHIN

IPC: G11C17/16 ,  G11C29/02 ,  G11C17/18

CPC classification number: G11C17/16 ,  G11C17/18 ,  G11C29/02 ,  G11C29/4401 ,  G11C29/789 ,  G11C2029/4402

Abstract: A semiconductor device including a first latch unit suitable for storing a first address of a first memory cell tested in a first cell array block, a second latch unit suitable for storing a second address of a second memory cell tested in a second cell array block, a first selector suitable for receiving a first selection signal or a second selection signal to output any one of the first address and the second address as a selected address, and a program controller suitable for determining whether the selected address has to be stored in a fuse array and to control an operation for programming the fuse array.

Abstract translation: 一种半导体器件，包括适于存储在第一单元阵列块中测试的第一存储单元的第一地址的第一锁存单元，适于存储在第二单元阵列块中测试的第二存储单元的第二地址的第二锁存单元， 适于接收第一选择信号或第二选择信号的第一选择器，以输出第一地址和第二地址中的任何一个作为所选择的地址;以及程序控制器，适于确定所选择的地址是否必须存储在保险丝中 阵列并控制用于编程保险丝阵列的操作。

公开(公告)号：US20220172772A1

公开(公告)日：2022-06-02

申请号：US17676644

申请日：2022-02-21

Applicant: SK hynix Inc.

Inventor： Se Won LEE ,  Tae Kyun SHIN ,  Jun Sang LEE

IPC: G11C11/406 ,  G11C11/4074

Abstract: An electronic device includes an internal mode control circuit suitable for generating a burst control signal, a blocking control signal and an internal voltage control signal based on a refresh cycle when an internal mode is performed in a self-refresh operation, a refresh control circuit suitable for generating a refresh signal for performing a refresh operation every refresh cycle when the self-refresh operation is performed, generating the refresh signal every set cycle based on the burst control signal when the internal mode is performed, and blocking the generation of the refresh signal based on the blocking control signal, and an internal voltage generation circuit suitable for adjusting a level of an internal voltage for the refresh operation based on the internal voltage control signal.

公开(公告)号：US20180090221A1

公开(公告)日：2018-03-29

申请号：US15434990

申请日：2017-02-16

Applicant: SK hynix Inc.

Inventor： Yong Sun KIM ,  Tae Kyun SHIN

IPC: G11C17/18 ,  G11C17/16 ,  G11C29/12

CPC classification number: G11C17/18 ,  G11C7/20 ,  G11C17/16 ,  G11C29/027 ,  G11C29/12 ,  G11C29/24 ,  G11C29/781

Abstract: A boot-up control circuit may be provided. The boot-up control circuit may include a fuse array including a one or more normal fuses and one or more dummy fuses. The boot-up control circuit may include a fuse array controller configured to determine whether or not to start a normal boot-up operation for the one or more normal fuses according to a comparison result between expected data and test fuse data output from the one or more dummy fuses through a test boot-up operation.

公开(公告)号：US20150380105A1

公开(公告)日：2015-12-31

申请号：US14526885

申请日：2014-10-29

Applicant: SK hynix Inc.

Inventor： Tae Kyun SHIN

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C17/16 ,  G11C29/4401

Abstract: The semiconductor system includes a controller and a semiconductor device. The controller outputs commands and receives an output datum to discriminate whether at least one of a plurality of fuse cells abnormally operates. The semiconductor device compares logic levels of a plurality of fuse data generated from the plurality of fuse cells with each other, thereby generating a flag signal enabled when at least one of the logic levels of the plurality of fuse data is different from the other logic levels while a boot-up operation is executed according to a combination of the commands. In addition, the semiconductor device outputs the flag signal as the output datum while a read operation is executed according to a combination of the commands.

Abstract translation: 半导体系统包括控制器和半导体器件。 控制器输出命令并接收输出数据，以区分多个熔丝单元中的至少一个是否异常操作。 半导体器件将从多个熔丝单元产生的多个熔丝数据的逻辑电平彼此进行比较，从而当多个熔丝数据的逻辑电平中的至少一个与其它逻辑电平不同时，产生使能的标志信号 同时根据命令的组合来执行启动操作。 此外，半导体器件在根据命令的组合执行读取操作时输出标志信号作为输出数据。

公开(公告)号：US20220406367A1

公开(公告)日：2022-12-22

申请号：US17480832

申请日：2021-09-21

Applicant: SK hynix Inc.

Inventor： Hyun Seung KIM ,  Ho Uk SONG ,  Tae Kyun SHIN ,  Min Jun CHOI ,  Duck Hwa HONG

IPC: G11C11/406 ,  G11C11/4076

Abstract: An electronic device includes an intelligent refresh control circuit generating an intelligent refresh pulse with a pulse that has a generation period that is adjusted based on the number of generations of an auto refresh signal during an intelligent refresh operation, and an internal refresh signal generation circuit outputting one of a self-refresh pulse including a pulse that is periodically generated by an enable signal during a self-refresh operation and the intelligent refresh pulse as an internal refresh signal.

公开(公告)号：US20180166144A1

公开(公告)日：2018-06-14

申请号：US15656138

申请日：2017-07-21

Applicant: SK hynix Inc.

Inventor： Hyeong Soo JEONG ,  Tae Kyun SHIN ,  Young Bo SHIM

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C7/10 ,  G11C8/06 ,  G11C17/16 ,  G11C2029/4402

Abstract: A semiconductor device includes an internal command generation circuit suitable for generating a first internal command, a second internal command, and a third internal command based on a command/address signal. The semiconductor device also includes a driving signal generation circuit suitable for enabling a fuse driving signal for reading fuse data from a nonvolatile memory circuit, where the fuse signal is enabled while the second internal command is inputted a predetermined number of times. Further included is an output circuit suitable for outputting the fuse data in response to the third internal command.