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公开(公告)号：US20180097482A1
公开(公告)日：2018-04-05
申请号：US15720335
申请日：2017-09-29
Applicant: Skyworks Solutions, Inc.
Inventor： Oleksandr Gorbachov , Qiang Li , Floyd Ashbaugh , Aydin Seyedi , Lothar Musiol , Lisette L. Zhang
CPC classification number: H03F3/193 , H03F1/0261 , H03F1/301 , H03F1/3205 , H03F2200/18 , H03F2200/451
Abstract: An RF power amplifier biasing circuit has a start ramp signal input, a main current source input, an auxiliary current source input, and a circuit output. A ramp-up capacitor is connected to the auxiliary current source input. A ramp-up switch transistor is connected to the start ramp signal input and is selectively thereby to connect the auxiliary current source input to the ramp-up capacitor. A buffer stage has an input connected to the ramp-up capacitor and an output connected to the main current source input at a sum node. A mirror transistor has a gate terminal corresponding to the circuit output and a source terminal connected to the sum node and to the gate terminal.
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公开(公告)号：US10320344B2
公开(公告)日：2019-06-11
申请号：US15720335
申请日：2017-09-29
Applicant: Skyworks Solutions, Inc.
Inventor： Oleksandr Gorbachov , Qiang Li , Floyd Ashbaugh , Aydin Seyedi , Lothar Musiol , Lisette L. Zhang
Abstract: An RF power amplifier biasing circuit has a start ramp signal input, a main current source input, an auxiliary current source input, and a circuit output. A ramp-up capacitor is connected to the auxiliary current source input. A ramp-up switch transistor is connected to the start ramp signal input and is selectively thereby to connect the auxiliary current source input to the ramp-up capacitor. A buffer stage has an input connected to the ramp-up capacitor and an output connected to the main current source input at a sum node. A mirror transistor has a gate terminal corresponding to the circuit output and a source terminal connected to the sum node and to the gate terminal.
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公开(公告)号：US09806679B2
公开(公告)日：2017-10-31
申请号：US14849936
申请日：2015-09-10
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Oleksandr Gorbachov , Qiang Li , Floyd Ashbaugh , Aydin Seyedi , Lothar Musiol , Lisette L. Zhang
CPC classification number: H03F3/193 , H03F1/0261 , H03F1/301 , H03F1/3205 , H03F2200/18 , H03F2200/451
Abstract: An RF power amplifier biasing circuit has a start ramp signal input, a main current source input, an auxiliary current source input, and a circuit output. A ramp-up capacitor is connected to the auxiliary current source input. A ramp-up switch transistor is connected to the start ramp signal input and is selectively thereby to connect the auxiliary current source input to the ramp-up capacitor. A buffer stage has an input connected to the ramp-up capacitor and an output connected to the main current source input at a sum node. A mirror transistor has a gate terminal corresponding to the circuit output and a source terminal connected to the sum node and to the gate terminal.
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公开(公告)号：US20190273473A1
公开(公告)日：2019-09-05
申请号：US16408139
申请日：2019-05-09
Applicant: Skyworks Solutions, Inc.
Inventor： Oleksandr Gorbachov , Qiang Li , Floyd Ashbaugh , Aydin Seyedi , Lothar Musiol , Lisette L. Zhang
Abstract: An RF power amplifier biasing circuit has a start ramp signal input, a main current source input, an auxiliary current source input, and a circuit output. A ramp-up capacitor is connected to the auxiliary current source input. A ramp-up switch transistor is connected to the start ramp signal input and is selectively thereby to connect the auxiliary current source input to the ramp-up capacitor. A buffer stage has an input connected to the ramp-up capacitor and an output connected to the main current source input at a sum node. A mirror transistor has a gate terminal corresponding to the circuit output and a source terminal connected to the sum node and to the gate terminal.
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