公开(公告)号：US09558801B2

公开(公告)日：2017-01-31

申请号：US14755935

申请日：2015-06-30

Applicant: SOCIONEXT INC.

Inventor： Hirotaka Takeno ,  Akio Yamamoto

IPC: G11C11/00 ,  G11C11/16 ,  G11C14/00 ,  H03K3/3562 ,  G11C13/00 ,  H03K19/18

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/0081 ,  G11C14/009 ,  H03K3/3562 ,  H03K19/18

Abstract: A data holding circuit includes: a latch circuit having a first terminal and a second terminal, a logical value held at the first terminal being changed according to a value to be held by the data holding circuit, and the second terminal holding an inverted logical value of the logical value held at the first terminal; and a storing circuit which stores the logical values held at the first terminal and the second terminal in response to a write signal, and sets the logical values held at the first terminal and the second terminal to the stored logical values in response to a read signal, wherein the storing circuit includes two Magnetic Tunnel Junction elements which are connected in series between the first terminal and the second terminal and in reverse directions to each other.

Abstract translation: 数据保持电路包括：具有第一端子和第二端子的锁存电路，保持在第一端子处的逻辑值根据由数据保持电路保持的值而改变，第二端子保持反相逻辑值 在第一个终端持有的逻辑价值; 以及存储电路，其响应于写信号存储保持在第一终端和第二终端的逻辑值，并且响应于读信号将保持在第一终端和第二终端的逻辑值设置为存储的逻辑值 其中，所述存储电路包括串联连接在所述第一端子和所述第二端子之间并且彼此相反方向的两个磁隧道结元件。