公开(公告)号：US20190033355A1

公开(公告)日：2019-01-31

申请号：US16002373

申请日：2018-06-07

申请人： SOCIONEXT INC.

发明人： Albert Hubert DORNER ,  Martin Wahle

IPC分类号： G01R25/08 ,  H03K5/14 ,  H03K5/26 ,  H03L7/085

摘要： The present disclosure relates to phase measurement circuitry operable based on a first clock signal having an intended clock frequency F1 and a second clock signal having an intended clock frequency F2, the circuitry comprising: a delay line configured to receive the first clock signal, the delay line comprising a plurality of delay units each configured to cause a propagation delay, and the plurality of delay units connected in series along the length of the delay line and defining a series of positions therebetween through which signal edges of the first clock signal propagate over time; an edge detector configured to sample the delay line at successive sample times based on the second clock signal and to record at each sample time the position of a given signal edge of the first clock signal along the delay line; and a phase angle determiner configured to determine a phase angle per delay unit based on successive recorded said positions.

公开(公告)号：US10914772B2

公开(公告)日：2021-02-09

申请号：US16002373

申请日：2018-06-07

申请人： SOCIONEXT INC.

发明人： Albert Hubert Dorner ,  Martin Wahle

IPC分类号： G01R25/08 ,  H03K5/14 ,  H03K5/26 ,  H03L7/085 ,  G01R25/00 ,  H03L7/22 ,  H03L7/08 ,  H03K5/00

摘要： The present disclosure relates to phase measurement circuitry operable based on a first clock signal having an intended clock frequency F1 and a second clock signal having an intended clock frequency F2, the circuitry comprising: a delay line configured to receive the first clock signal, the delay line comprising a plurality of delay units each configured to cause a propagation delay, and the plurality of delay units connected in series along the length of the delay line and defining a series of positions therebetween through which signal edges of the first clock signal propagate over time; an edge detector configured to sample the delay line at successive sample times based on the second clock signal and to record at each sample time the position of a given signal edge of the first clock signal along the delay line; and a phase angle determiner configured to determine a phase angle per delay unit based on successive recorded said positions.