公开(公告)号：US20180076809A1

公开(公告)日：2018-03-15

申请号：US15813939

申请日：2017-11-15

Applicant: SOCIONEXT INC.

Inventor： Hajime OHMI ,  Osamu Uno ,  Masahiro Iwamoto ,  Yuichi Itonaga

IPC: H03K17/081 ,  H03K19/0185 ,  H03K19/003

CPC classification number: H03K17/08104 ,  H03K19/00315 ,  H03K19/018521 ,  H03K19/018592

Abstract: A semiconductor apparatus includes an internal circuit connected to a first power line to which a first power voltage is applied; a transistor including a first terminal, which is connected to a node to which an input voltage is applied, a second terminal connected to the internal circuit, and a control terminal to which a control voltage is applied; and a voltage control circuit, which is connected to the node, generating the control voltage. Further, the voltage control circuit includes a step-down circuit generating an internal voltage by lowering the input voltage applied to the node, and a switching circuit, which is connected to the first power line, generating the control voltage based on the first power voltage and the internal voltage.

公开(公告)号：US20170012612A1

公开(公告)日：2017-01-12

申请号：US15173293

申请日：2016-06-03

Applicant: SOCIONEXT INC.

Inventor： Tomohiko KOTO ,  Kenichi Konishi ,  Osamu Uno

IPC: H03K3/356

CPC classification number: H03K3/356086 ,  H03K3/35613 ,  H03K3/356165 ,  H03K3/356182

Abstract: A level conversion circuit includes: first P-ch and N-ch transistors and second P-ch and N-ch transistors respectively connected in series between first and second power sources; third and fourth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and the drain of the first and second P-ch transistors; and fifth and sixth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and a third power source, wherein differential input signals are applied to the gates of the first and second N-ch transistors, a bias voltage is applied to the gates of the third and fourth P-ch transistors, the gate of the fifth and sixth P-ch transistors are respectively connected to connection nodes of the first P-ch and N-ch transistors the second P-ch and N-ch transistors.

Abstract translation: 电平转换电路包括：分别串联连接在第一和第二电源之间的第一P-ch和N-ch晶体管和第二P-ch和N-ch晶体管; 分别连接在第二和第一P-ch晶体管的栅极和第一和第二P-ch晶体管的漏极之间的第三和第四Pch晶体管; 以及分别连接在第二和第一P-ch晶体管的栅极和第三电源之间的第五和第六Pch晶体管，其中差分输入信号施加到第一和第二N沟道晶体管的栅极，偏置电压 施加到第三和第四P-ch晶体管的栅极，第五和第六Pch晶体管的栅极分别连接到第一P-ch和N-ch晶体管的连接节点，第二P-ch和N -ch晶体管。

公开(公告)号：US11595044B2

公开(公告)日：2023-02-28

申请号：US17244821

申请日：2021-04-29

Applicant: SOCIONEXT INC.

Inventor： Osamu Uno

IPC: H03K19/094 ,  H03K17/687 ,  H03K19/0185

Abstract: An input circuit includes an input buffer circuit using a first node as an input and a second node as an output, an N-type transistor having a source coupled to the input terminal, a drain coupled to the first node, and a gate coupled to a power supply, and a pull-up circuit provided between the first node and the power supply. The pull-up circuit is configured to make the power supply and the first node conducive with each other for a predetermined period when the input signal transitions from low to high and not to make the power supply and the first node conductive with each other when the input signal transitions from high to low.

公开(公告)号：US09991882B2

公开(公告)日：2018-06-05

申请号：US15813939

申请日：2017-11-15

Applicant: SOCIONEXT INC.

Inventor： Hajime Ohmi ,  Osamu Uno ,  Masahiro Iwamoto ,  Yuichi Itonaga

IPC: H03K17/081 ,  H03K9/04 ,  H03K19/0185 ,  H03K19/003

CPC classification number: H03K17/08104 ,  H03K19/00315 ,  H03K19/018521 ,  H03K19/018592

Abstract: A semiconductor apparatus includes an internal circuit connected to a first power line to which a first power voltage is applied; a transistor including a first terminal, which is connected to a node to which an input voltage is applied, a second terminal connected to the internal circuit, and a control terminal to which a control voltage is applied; and a voltage control circuit, which is connected to the node, generating the control voltage. Further, the voltage control circuit includes a step-down circuit generating an internal voltage by lowering the input voltage applied to the node, and a switching circuit, which is connected to the first power line, generating the control voltage based on the first power voltage and the internal voltage.

公开(公告)号：US09853636B2

公开(公告)日：2017-12-26

申请号：US14741911

申请日：2015-06-17

Applicant: SOCIONEXT INC.

Inventor： Hajime Ohmi ,  Osamu Uno ,  Masahiro Iwamoto ,  Yuichi Itonaga

IPC: H03K17/081 ,  H03K19/003 ,  H03K19/0185

CPC classification number: H03K17/08104 ,  H03K19/00315 ,  H03K19/018521 ,  H03K19/018592

Abstract: A semiconductor apparatus includes an internal circuit connected to a first power line to which a first power voltage is applied; a transistor including a first terminal, which is connected to a node to which an input voltage is applied, a second terminal connected to the internal circuit, and a control terminal to which a control voltage is applied; and a voltage control circuit, which is connected to the node, generating the control voltage. Further, the voltage control circuit includes a step-down circuit generating an internal voltage by lowering the input voltage applied to the node, and a switching circuit, which is connected to the first power line, generating the control voltage based on the first power voltage and the internal voltage.

公开(公告)号：US09780762B2

公开(公告)日：2017-10-03

申请号：US15173293

申请日：2016-06-03

Applicant: SOCIONEXT INC.

Inventor： Tomohiko Koto ,  Kenichi Konishi ,  Osamu Uno

IPC: H03L5/00 ,  H03K3/356

CPC classification number: H03K3/356086 ,  H03K3/35613 ,  H03K3/356165 ,  H03K3/356182

Abstract: A level conversion circuit includes: first P-ch and N-ch transistors and second P-ch and N-ch transistors respectively connected in series between first and second power sources; third and fourth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and the drain of the first and second P-ch transistors; and fifth and sixth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and a third power source, wherein differential input signals are applied to the gates of the first and second N-ch transistors, a bias voltage is applied to the gates of the third and fourth P-ch transistors, the gate of the fifth and sixth P-ch transistors are respectively connected to connection nodes of the first P-ch and N-ch transistors the second P-ch and N-ch transistors.