公开(公告)号：US11003611B2

公开(公告)日：2021-05-11

申请号：US17037431

申请日：2020-09-29

Applicant: SOCIONEXT INC.

Inventor： Eiichi Nimoda ,  Seiji Goto ,  Satoru Okamoto ,  Shuichi Yamane ,  Yasuo Nishiguchi

IPC: G06F12/02 ,  G06F13/40 ,  G06F12/10 ,  G06F13/16 ,  G06F13/42

Abstract: A bridge apparatus includes slave circuits connected to each other via a bus. Each of the slave circuits is connected to one of master apparatuses, function as a slave for the master apparatus connected thereto, and performs communication in accordance with a protocol in which the number of masters in a system is restricted. Addresses of memories are respectively set in the slave circuits, and the memories are connected to the master apparatuses to which the slave circuits are respectively connected. When a first master apparatus accesses a memory connected to a second master apparatus by specifying a first address of the memory, the bridge apparatus causes the first master apparatus and the second master apparatus to communicate via a first slave circuit, a second slave circuit in which an address corresponding to the first address is set, and the bus, based on the addresses of the memories.

公开(公告)号：US20210011873A1

公开(公告)日：2021-01-14

申请号：US17037431

申请日：2020-09-29

Applicant: SOCIONEXT INC.

Inventor： Eiichi Nimoda ,  Seiji Goto ,  Satoru Okamoto ,  Shuichi Yamane ,  Yasuo Nishiguchi

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G06F12/10

Abstract: A bridge apparatus includes slave circuits connected to each other via a bus. Each of the slave circuits is connected to one of master apparatuses, function as a slave for the master apparatus connected thereto, and performs communication in accordance with a protocol in which the number of masters in a system is restricted. Addresses of memories are respectively set in the slave circuits, and the memories are connected to the master apparatuses to which the slave circuits are respectively connected. When a first master apparatus accesses a memory connected to a second master apparatus by specifying a first address of the memory, the bridge apparatus causes the first master apparatus and the second master apparatus to communicate via a first slave circuit, a second slave circuit in which an address corresponding to the first address is set, and the bus, based on the addresses of the memories.