公开(公告)号：US11550962B2

公开(公告)日：2023-01-10

申请号：US16867911

申请日：2020-05-06

Applicant: SOCIONEXT INC.

Inventor： Seiji Goto ,  Jun Kamada ,  Taiji Tamiya

IPC: G06F12/16 ,  G06F12/14 ,  G06F11/00 ,  G06F21/74 ,  G06F21/52 ,  G06F21/55 ,  G06F21/57 ,  G06F21/64 ,  G06F21/71 ,  G06F21/72 ,  G06F21/70 ,  G06F21/53 ,  G06F12/1027 ,  G06F13/24

Abstract: The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

公开(公告)号：US11003611B2

公开(公告)日：2021-05-11

申请号：US17037431

申请日：2020-09-29

Applicant: SOCIONEXT INC.

Inventor： Eiichi Nimoda ,  Seiji Goto ,  Satoru Okamoto ,  Shuichi Yamane ,  Yasuo Nishiguchi

IPC: G06F12/02 ,  G06F13/40 ,  G06F12/10 ,  G06F13/16 ,  G06F13/42

Abstract: A bridge apparatus includes slave circuits connected to each other via a bus. Each of the slave circuits is connected to one of master apparatuses, function as a slave for the master apparatus connected thereto, and performs communication in accordance with a protocol in which the number of masters in a system is restricted. Addresses of memories are respectively set in the slave circuits, and the memories are connected to the master apparatuses to which the slave circuits are respectively connected. When a first master apparatus accesses a memory connected to a second master apparatus by specifying a first address of the memory, the bridge apparatus causes the first master apparatus and the second master apparatus to communicate via a first slave circuit, a second slave circuit in which an address corresponding to the first address is set, and the bus, based on the addresses of the memories.

公开(公告)号：US20200302069A1

公开(公告)日：2020-09-24

申请号：US16899256

申请日：2020-06-11

Applicant: SOCIONEXT INC.

Inventor： Seiji Goto ,  Eiichi NIMODA

IPC: G06F21/60 ,  G06F9/4401 ,  G06F11/07

Abstract: In a processing apparatus having semiconductor integrated circuits, a first status monitoring circuit included in a first semiconductor integrated circuit is configured to instruct a plurality of second semiconductor integrated circuits to transmit status information indicating statuses of the plurality of second semiconductor integrated circuits. When a second status monitoring circuit included in each of the plurality of second semiconductor integrated circuits receives the instruction for transmission of the corresponding status information, the second status monitoring circuit transmits encrypted information in which the status information is encrypted to the first semiconductor integrated circuit.

公开(公告)号：US10303901B2

公开(公告)日：2019-05-28

申请号：US15340061

申请日：2016-11-01

Applicant: Socionext Inc.

Inventor： Seiji Goto ,  Jun Kamada ,  Taiji Tamiya

IPC: G11C7/00 ,  G06F17/30 ,  G06F13/00 ,  G06F12/14 ,  G06F12/00 ,  G06F7/04 ,  G06F21/74 ,  G06F21/52 ,  G06F21/55 ,  G06F21/57 ,  G06F21/64 ,  G06F21/71 ,  G06F21/72 ,  G06F21/70 ,  G06F21/53 ,  G06F12/1027 ,  G06F13/24

Abstract: The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

公开(公告)号：US09672384B2

公开(公告)日：2017-06-06

申请号：US14091483

申请日：2013-11-27

Applicant: Socionext Inc.

Inventor： Seiji Goto ,  Jun Kamada ,  Taiji Tamiya

IPC: G06F11/30 ,  G06F12/14 ,  G06F21/70 ,  G06F21/52 ,  G06F21/55 ,  G06F21/57 ,  G06F21/64 ,  G06F21/71 ,  G06F21/72

CPC classification number: G06F21/70 ,  G06F12/1027 ,  G06F12/1408 ,  G06F13/24 ,  G06F21/52 ,  G06F21/53 ,  G06F21/554 ,  G06F21/575 ,  G06F21/64 ,  G06F21/71 ,  G06F21/72 ,  G06F21/74 ,  G06F2212/1052 ,  G06F2212/682

Abstract: The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

公开(公告)号：US09652635B2

公开(公告)日：2017-05-16

申请号：US14091475

申请日：2013-11-27

Applicant: Socionext Inc.

Inventor： Seiji Goto ,  Jun Kamada ,  Taiji Tamiya

IPC: G06F12/14 ,  G06F11/30 ,  G06F21/70 ,  G06F21/52 ,  G06F21/55 ,  G06F21/57 ,  G06F21/64 ,  G06F21/71 ,  G06F21/72

CPC classification number: G06F21/70 ,  G06F12/1027 ,  G06F12/1408 ,  G06F13/24 ,  G06F21/52 ,  G06F21/53 ,  G06F21/554 ,  G06F21/575 ,  G06F21/64 ,  G06F21/71 ,  G06F21/72 ,  G06F21/74 ,  G06F2212/1052 ,  G06F2212/682

Abstract: The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

公开(公告)号：US20210011873A1

公开(公告)日：2021-01-14

申请号：US17037431

申请日：2020-09-29

Applicant: SOCIONEXT INC.

Inventor： Eiichi Nimoda ,  Seiji Goto ,  Satoru Okamoto ,  Shuichi Yamane ,  Yasuo Nishiguchi

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G06F12/10

Abstract: A bridge apparatus includes slave circuits connected to each other via a bus. Each of the slave circuits is connected to one of master apparatuses, function as a slave for the master apparatus connected thereto, and performs communication in accordance with a protocol in which the number of masters in a system is restricted. Addresses of memories are respectively set in the slave circuits, and the memories are connected to the master apparatuses to which the slave circuits are respectively connected. When a first master apparatus accesses a memory connected to a second master apparatus by specifying a first address of the memory, the bridge apparatus causes the first master apparatus and the second master apparatus to communicate via a first slave circuit, a second slave circuit in which an address corresponding to the first address is set, and the bus, based on the addresses of the memories.

公开(公告)号：US10853287B2

公开(公告)日：2020-12-01

申请号：US16392240

申请日：2019-04-23

Applicant: SOCIONEXT INC.

Inventor： Seiji Goto ,  Eiichi Nimoda ,  Satoru Okamoto

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/38

Abstract: Processing by an information processing system is speeded up. A first semiconductor integrated circuit designates a first address of a memory connected to a second semiconductor integrated circuit that is a data transmission destination, based on first memory map information in which addresses of memories respectively used by the semiconductor integrated circuits are defined, converts the first address to a second address of the memory defined in second memory map information referred to by the data transmission destination, and outputs the second address and transmission data by using a PCIe interface. A switch transfers the second address and the transmission data to the data transmission destination by using PCIe interfaces. The data transmission destination receives the second address and the transmission data by using a PCIe interface and writes the transmission data into the reception buffer region of the memory corresponding to the second address.

公开(公告)号：US11537730B2

公开(公告)日：2022-12-27

申请号：US16899256

申请日：2020-06-11

Applicant: SOCIONEXT INC.

Inventor： Seiji Goto ,  Eiichi Nimoda

IPC: G06F21/60 ,  G06F9/4401 ,  G06F11/07

Abstract: In a processing apparatus having semiconductor integrated circuits, a first status monitoring circuit included in a first semiconductor integrated circuit is configured to instruct a plurality of second semiconductor integrated circuits to transmit status information indicating statuses of the plurality of second semiconductor integrated circuits. When a second status monitoring circuit included in each of the plurality of second semiconductor integrated circuits receives the instruction for transmission of the corresponding status information, the second status monitoring circuit transmits encrypted information in which the status information is encrypted to the first semiconductor integrated circuit.

公开(公告)号：US10997298B2

公开(公告)日：2021-05-04

申请号：US16259884

申请日：2019-01-28

Applicant: Socionext Inc.

Inventor： Kazuya Asano ,  Yuya Ueno ,  Seiji Goto

IPC: G06F21/57 ,  H04L9/08 ,  G06F9/4401 ,  G06F15/177 ,  G06F21/85

Abstract: A semiconductor integrated circuit generates second boot code by encrypting first boot code, and transmits, based on route information indicating a delivery route of the second boot code, encrypted data including the second boot code to a first destination via a network. A different semiconductor integrated circuit is the first destination, and receives the encrypted data via the network and generates third boot code by decrypting the second boot code.