公开(公告)号：US20210234030A1

公开(公告)日：2021-07-29

申请号：US16969437

申请日：2019-10-21

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng SUN ,  Siyang LIU ,  Sheng LI ,  Chi ZHANG ,  Xinyi TAO ,  Ningbo LI ,  Longxing SHI

IPC: H01L29/778

Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.

公开(公告)号：US20220069115A1

公开(公告)日：2022-03-03

申请号：US17417663

申请日：2019-12-19

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Siyang LIU ,  Chi ZHANG ,  Kui XIAO ,  Guipeng SUN ,  Dejin WANG ,  Jiaxing WEI ,  Li LU ,  Weifeng SUN ,  Shengli LU

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207

Abstract: A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

公开(公告)号：US20210336009A1

公开(公告)日：2021-10-28

申请号：US16486494

申请日：2018-09-25

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng SUN ,  Siyang LIU ,  Lizhi TANG ,  Sheng LI ,  Chi ZHANG ,  Jiaxing WEI ,  Shengli LU ,  Longxing SHI

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/78

Abstract: The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.

公开(公告)号：US20220367716A1

公开(公告)日：2022-11-17

申请号：US17762929

申请日：2021-01-20

Applicant: SOUTHEAST UNIVERSITY

Inventor： Siyang LIU ,  Weifeng SUN ,  Chi ZHANG ,  Shuxuan XIN ,  Shen LI ,  Le QIAN ,  Chen GE ,  Longxing SHI

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/812 ,  H01L29/778

Abstract: The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region. The dielectric layer, the heavily doped semiconductor layer, the metal gate electrode and the source metal electrode only exist in the cell region, and the passivation layer of the terminal region extends upwards and is wrapped outside the channel layer. This structure can increase a threshold voltage of the device, improve the blocking characteristics of the device and reduce the size of a gate capacitance.