公开(公告)号：US20220115532A1

公开(公告)日：2022-04-14

申请号：US17417677

申请日：2019-12-23

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Weifeng SUN ,  Rongcheng LOU ,  Kui XIAO ,  Feng LIN ,  Jiaxing WEI ,  Sheng LI ,  Siyang LIU ,  Shengli LU ,  Longxing SHI

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L21/04 ,  H01L29/66

Abstract: A power semiconductor device includes a substrate; drain metal; a drift region; a base region; a gate structure; a first conductive type doped region contacting the base region on the side of the base region distant from the gate structure; a source region provided in the base region and between the first conductive type doped region and the gate structure; contact metal that is provided on the first conductive type doped region and forms a contact barrier having rectifying characteristics together with the first conductive type doped region below; and source metal wrapping the contact metal and contacting the source region.

公开(公告)号：US20180174942A1

公开(公告)日：2018-06-21

申请号：US15576850

申请日：2016-01-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Siyang LIU ,  Ning WANG ,  Jiaxing WEI ,  Chao LIU ,  Weifeng SUN ,  Shengli LU ,  Longxing SHI

IPC: H01L23/367 ,  H01L25/18 ,  H01L23/31 ,  H01L23/495 ,  H01L25/16

CPC classification number: H01L23/3675 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48175 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/1306 ,  H01L2924/1426 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power module includes an insulating resin, a driving chip, a plurality of power chips, and a plurality of metal electrode contacts. The driving chip, the power chips, and the metal electrode contacts are electrically connected through a metal lead according to a predetermined circuit. A plurality of metal heat dissipating disks used for heat dissipation of the power chips and a driving chip lead frame are disposed at the bottom of the insulating resin. A plurality of metal power chip lead frames are disposed on the metal heat dissipating disks, the power chips are disposed on the power chip lead frames, and the drain electrodes of the power chips are electrically connected to the metal heat dissipating disks.

公开(公告)号：US20230019004A1

公开(公告)日：2023-01-19

申请号：US17762206

申请日：2020-09-25

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jiaxing WEI ,  Qichao WANG ,  Kui XIAO ,  Dejin WANG ,  Li LU ,  Ling YANG ,  Ran YE ,  Siyang LIU ,  Weifeng SUN ,  Longxing SHI

IPC: H01L29/78

Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.

公开(公告)号：US20220069115A1

公开(公告)日：2022-03-03

申请号：US17417663

申请日：2019-12-19

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Siyang LIU ,  Chi ZHANG ,  Kui XIAO ,  Guipeng SUN ,  Dejin WANG ,  Jiaxing WEI ,  Li LU ,  Weifeng SUN ,  Shengli LU

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207

Abstract: A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

公开(公告)号：US20210336009A1

公开(公告)日：2021-10-28

申请号：US16486494

申请日：2018-09-25

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng SUN ,  Siyang LIU ,  Lizhi TANG ,  Sheng LI ,  Chi ZHANG ,  Jiaxing WEI ,  Shengli LU ,  Longxing SHI

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/78

Abstract: The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.