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    SELF-ADAPTIVE SYNCHRONOUS RECTIFICATION CONTROL SYSTEM AND METHOD OF ACTIVE CLAMP FLYBACK CONVERTER
    2.
    发明申请
    SELF-ADAPTIVE SYNCHRONOUS RECTIFICATION CONTROL SYSTEM AND METHOD OF ACTIVE CLAMP FLYBACK CONVERTER 有权

    公开(公告)号：US20210194375A1

    公开(公告)日：2021-06-24

    申请号：US16617508

    申请日：2018-09-28

    申请人： SOUTHEAST UNIVERSITY

    发明人： Qinsong QIAN ,  Shengyou XU ,  Qi LIU ,  Weifeng SUN ,  Shengli LU ,  Longxing SHI

    IPC分类号： H02M3/335 ,  H02M1/08

    摘要： The invention discloses a self-adaptive synchronous rectification control system and a self-adaptive synchronous rectification control method of an active clamp flyback converter. The control system comprises a sampling and signal processing circuit, a control circuit with a microcontroller as a core and a gate driver. According to the control method, a switching-on state, an early switching-off state, a late switching-off state and an exact switching-off state of a secondary synchronous rectifier of the active clamp flyback converter can be directly detected, and the synchronous rectifier and a switching-on time of the synchronous rectifier in next cycle can be controlled according to a detection result. After several cycles of self-adaptive control, the synchronous rectifier enters the exact switching-on state, thus avoiding oscillation of an output waveform of the active clamp flyback converter.

    GATE DRIVE CIRCUIT FOR REDUCING REVERSE RECOVERY CURRENT OF POWER DEVICE
    4.
    发明申请
    GATE DRIVE CIRCUIT FOR REDUCING REVERSE RECOVERY CURRENT OF POWER DEVICE 有权

    公开(公告)号：US20210218396A1

    公开(公告)日：2021-07-15

    申请号：US17044623

    申请日：2020-04-15

    申请人： SOUTHEAST UNIVERSITY

    发明人： Jing ZHU ,  Weifeng SUN ,  Bowei YANG ,  Siyuan YU ,  Yangyang LU ,  Longxing SHI ,  Shengli LU

    IPC分类号： H03K17/687 ,  H03K19/20

    摘要： The present invention discloses a gate drive circuit for reducing a reverse recovery current of a power device, and belongs to the field of basic electronic circuit technologies. The gate drive circuit includes a high-voltage LDMOS transistor, a diode forming a freewheeling path when the diode is turned on or a low-voltage MOS transistor in anti-parallel connection with a body diode, and a voltage detection circuit. When the power device is turned off, a freewheeling current produced by an inductive load flows through a freewheeling diode, the voltage detection circuit detects that the freewheeling diode is turned on, and an output signal is processed by a control circuit, to cause the drive circuit to output a high level, so that channels of the power device and the high-voltage LDMOS transistor are turned on, the freewheeling current flows through the conductive channels, almost not through the freewheeling diode, and there is no reverse recovery current in the freewheeling diode at this time, thereby reducing the reverse recovery current of the power device.

    GRAPHENE CHANNEL SILICON CARBIDE POWER SEMICONDUCTOR TRANSISTOR
    6.
    发明申请
    GRAPHENE CHANNEL SILICON CARBIDE POWER SEMICONDUCTOR TRANSISTOR 有权

    公开(公告)号：US20210336009A1

    公开(公告)日：2021-10-28

    申请号：US16486494

    申请日：2018-09-25

    申请人： SOUTHEAST UNIVERSITY

    发明人： Weifeng SUN ,  Siyang LIU ,  Lizhi TANG ,  Sheng LI ,  Chi ZHANG ,  Jiaxing WEI ,  Shengli LU ,  Longxing SHI

    IPC分类号： H01L29/16 ,  H01L29/06 ,  H01L29/78

    摘要： The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.

    LATERAL INSULATED GATE BIPOLAR TRANSISTOR WITH LOW TURN-ON OVERSHOOT CURRENT
    7.
    发明申请
    LATERAL INSULATED GATE BIPOLAR TRANSISTOR WITH LOW TURN-ON OVERSHOOT CURRENT 有权

    公开(公告)号：US20220157975A1

    公开(公告)日：2022-05-19

    申请号：US17606216

    申请日：2020-03-31

    申请人： SOUTHEAST UNIVERSITY

    发明人： Jing ZHU ,  Ankang LI ,  Long ZHANG ,  Weifeng SUN ,  Shengli LU ,  Longxing SHI

    IPC分类号： H01L29/739 ,  H01L29/10

    摘要： A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer. The polysilicon gate includes a first gate located above the surface of the P-type body region and a second gate located above the pinch-off region and the N-type drift region. The first gate is connected to a first gate resistor, and the second gate is connected to a second gate resistor.

    DEEP NEURAL NETWORK HARDWARE ACCELERATOR BASED ON POWER EXPONENTIAL QUANTIZATION
    8.
    发明申请
    DEEP NEURAL NETWORK HARDWARE ACCELERATOR BASED ON POWER EXPONENTIAL QUANTIZATION 有权

    公开(公告)号：US20210357736A1

    公开(公告)日：2021-11-18

    申请号：US17284480

    申请日：2020-01-09

    申请人： SOUTHEAST UNIVERSITY

    发明人： Shengli LU ,  Wei PANG ,  Ruili WU ,  Yingbo FAN ,  Hao LIU ,  Cheng HUANG

    IPC分类号： G06N3/063 ,  G06F9/50 ,  G06F5/01 ,  G06F7/556 ,  G06F7/552

    摘要： A deep neural network hardware accelerator comprises: an AXI-4 bus interface, an input cache area, an output cache area, a weighting cache area, a weighting index cache area, an encoding module, a configurable state controller module, and a PE array. The input cache area and the output cache area are designed as a line cache structure; an encoder encodes weightings according to an ordered quantization set, the quantization set storing the possible value of the absolute value of all of the weightings after quantization. During the calculation of the accelerator, the PE unit reads data from the input cache area and the weighting index cache area to perform shift calculation, and sends the calculation result to the output cache area. The accelerator uses shift operations to replace floating point multiplication operations, reducing the requirements for computing resources, storage resources, and communication bandwidth, and increasing the calculation efficiency of the accelerator.