公开(公告)号：US20180262186A1

公开(公告)日：2018-09-13

申请号：US15779432

申请日：2017-01-23

Applicant: SOUTHEAST UNIVERSITY ,  SOUTHEAST UNIVERSITY-WUXI INTEGRATED CIRCUIT TECHNOLOGY RESEARCH INSTITUTE

Inventor： Weifeng SUN ,  Yunwu ZHANG ,  Kuo YU ,  Jing ZHU ,  Shen XU ,  Qinsong QIAN ,  Siyang LIU ,  Shengli LU ,  Longxing SHI

IPC: H03K17/06 ,  H03K17/687 ,  H03K17/16

CPC classification number: H03K17/063 ,  H01L27/0727 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/7835 ,  H03K17/162 ,  H03K17/6871 ,  H03K19/0185 ,  H03K2217/0063 ,  H03K2217/0081

Abstract: Parasitic high-voltage diodes implemented by integration technology in a high-voltage level shift circuit are used for charging a bootstrap capacitor CB, wherein a power supply end of the high voltage level shift circuit is a high-side floating power supply VB, and a reference ground is a floating voltage PGD that is controlled by a bootstrap control circuit. A first parasitic diode DB1 and a second parasitic diode DB2 are provided between the VB and the PGD. The bootstrap control circuit is controlled by a high-side signal and a low-side signal.

公开(公告)号：US20220115532A1

公开(公告)日：2022-04-14

申请号：US17417677

申请日：2019-12-23

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Weifeng SUN ,  Rongcheng LOU ,  Kui XIAO ,  Feng LIN ,  Jiaxing WEI ,  Sheng LI ,  Siyang LIU ,  Shengli LU ,  Longxing SHI

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L21/04 ,  H01L29/66

Abstract: A power semiconductor device includes a substrate; drain metal; a drift region; a base region; a gate structure; a first conductive type doped region contacting the base region on the side of the base region distant from the gate structure; a source region provided in the base region and between the first conductive type doped region and the gate structure; contact metal that is provided on the first conductive type doped region and forms a contact barrier having rectifying characteristics together with the first conductive type doped region below; and source metal wrapping the contact metal and contacting the source region.

公开(公告)号：US20210234030A1

公开(公告)日：2021-07-29

申请号：US16969437

申请日：2019-10-21

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng SUN ,  Siyang LIU ,  Sheng LI ,  Chi ZHANG ,  Xinyi TAO ,  Ningbo LI ,  Longxing SHI

IPC: H01L29/778

Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.

公开(公告)号：US20240266430A1

公开(公告)日：2024-08-08

申请号：US18577714

申请日：2022-12-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Long ZHANG ,  Weifeng SUN ,  Siyang LIU ,  Jie MA ,  Peigang LIU ,  Longxing SHI

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L29/207

CPC classification number: H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/207

Abstract: An enhancement-mode N-channel and P-channel GaN device integration structure comprises a substrate, wherein an Al—N nucleating layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer are sequentially arranged on the substrate, and the AlGaN barrier layer and the GaN channel layer are divided by an isolation layer; a P-channel device is arranged on one side of the isolation layer and comprises a first P-GaN layer, a first GaN isolation layer and a first P+-GaN layer are sequentially arranged on the first P-GaN layer, a first source, a first gate and a first drain are arranged on the first P+-GaN layer, the first gate is inlaid in the first P+-GaN layer, and a gate dielectric layer is arranged between the first gate and the first P+-GaN layer; and an N-channel device is arranged on the other side of the isolation layer.

公开(公告)号：US20250056834A1

公开(公告)日：2025-02-13

申请号：US18722930

申请日：2022-11-30

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO LTD.

Inventor： Long ZHANG ,  Nailong HE ,  Yongjiu CUI ,  Sen ZHANG ,  Xiaona WANG ,  Feng LIN ,  Jie MA ,  Siyang LIU ,  Weifeng SUN

IPC: H01L29/78 ,  H01L21/266 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

Abstract: A manufacturing method for a P-type laterally diffused metal oxide semiconductor device includes: forming a N-type buried layer in a substrate, forming a P-type region located on the N-type buried layer, and forming a mask layer located on the P-type region; patterning the mask layer to form at least two injection windows; performing N-type ion implantation by the at least two injection windows; forming an oxide layer; removing the mask layer; performing P-type ion implantation on the P-type region to form a P-type doped region; diffusing the P-type doped region to form a drift region and two P-type well regions, diffusing the high-voltage N-well doped region to form a high-voltage N-type well region, and diffusing the low-voltage N-well doped region to form a low-voltage N-type well region; and forming a source doped region, a drain doped region, and a gate.

公开(公告)号：US20230019004A1

公开(公告)日：2023-01-19

申请号：US17762206

申请日：2020-09-25

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jiaxing WEI ,  Qichao WANG ,  Kui XIAO ,  Dejin WANG ,  Li LU ,  Ling YANG ,  Ran YE ,  Siyang LIU ,  Weifeng SUN ,  Longxing SHI

IPC: H01L29/78

Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.

公开(公告)号：US20220069115A1

公开(公告)日：2022-03-03

申请号：US17417663

申请日：2019-12-19

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Siyang LIU ,  Chi ZHANG ,  Kui XIAO ,  Guipeng SUN ,  Dejin WANG ,  Jiaxing WEI ,  Li LU ,  Weifeng SUN ,  Shengli LU

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207

Abstract: A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

公开(公告)号：US20210336009A1

公开(公告)日：2021-10-28

申请号：US16486494

申请日：2018-09-25

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng SUN ,  Siyang LIU ,  Lizhi TANG ,  Sheng LI ,  Chi ZHANG ,  Jiaxing WEI ,  Shengli LU ,  Longxing SHI

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/78

Abstract: The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.

公开(公告)号：US20240222473A1

公开(公告)日：2024-07-04

申请号：US18684175

申请日：2022-12-20

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

Inventor： Feng LIN ,  Chaoqi XU ,  Shuxian CHEN ,  Chunxu LI ,  Li LU ,  Siyang LIU ,  Weifeng SUN

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66734 ,  H01L21/2251 ,  H01L29/0619 ,  H01L29/41741 ,  H01L29/7813

Abstract: The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.

公开(公告)号：US20220367716A1

公开(公告)日：2022-11-17

申请号：US17762929

申请日：2021-01-20

Applicant: SOUTHEAST UNIVERSITY

Inventor： Siyang LIU ,  Weifeng SUN ,  Chi ZHANG ,  Shuxuan XIN ,  Shen LI ,  Le QIAN ,  Chen GE ,  Longxing SHI

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/812 ,  H01L29/778

Abstract: The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region. The dielectric layer, the heavily doped semiconductor layer, the metal gate electrode and the source metal electrode only exist in the cell region, and the passivation layer of the terminal region extends upwards and is wrapped outside the channel layer. This structure can increase a threshold voltage of the device, improve the blocking characteristics of the device and reduce the size of a gate capacitance.