公开(公告)号：US12051742B1

公开(公告)日：2024-07-30

申请号：US18577714

申请日：2022-12-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Long Zhang ,  Weifeng Sun ,  Siyang Liu ,  Jie Ma ,  Peigang Liu ,  Longxing Shi

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L29/207 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

Abstract: An enhancement-mode N-channel and P-channel GaN device integration structure comprises a substrate, wherein an Al—N nucleating layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer are sequentially arranged on the substrate, and the AlGaN barrier layer and the GaN channel layer are divided by an isolation layer; a P-channel device is arranged on one side of the isolation layer and comprises a first P-GaN layer, a first GaN isolation layer and a first P+-GaN layer are sequentially arranged on the first P-GaN layer, a first source, a first gate and a first drain are arranged on the first P+-GaN layer, the first gate is inlaid in the first P+-GaN layer, and a gate dielectric layer is arranged between the first gate and the first P+-GaN layer; and an N-channel device is arranged on the other side of the isolation layer.

公开(公告)号：US11367785B2

公开(公告)日：2022-06-21

申请号：US17606216

申请日：2020-03-31

Applicant: SOUTHEAST UNIVERSITY

Inventor： Jing Zhu ,  Ankang Li ,  Long Zhang ,  Weifeng Sun ,  Shengli Lu ,  Longxing Shi

IPC: H01L29/73 ,  H01L29/739 ,  H01L29/10

Abstract: A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer. The polysilicon gate includes a first gate located above the surface of the P-type body region and a second gate located above the pinch-off region and the N-type drift region. The first gate is connected to a first gate resistor, and the second gate is connected to a second gate resistor.

公开(公告)号：US12119395B2

公开(公告)日：2024-10-15

申请号：US17762212

申请日：2020-08-26

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Long Zhang ,  Jie Ma ,  Yan Gu ,  Sen Zhang ,  Jing Zhu ,  Jinli Gong ,  Weifeng Sun ,  Longxing Shi

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7394 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/1095

Abstract: An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.

公开(公告)号：US12046594B1

公开(公告)日：2024-07-23

申请号：US18638735

申请日：2024-04-18

Applicant: SOUTHEAST UNIVERSITY

Inventor： Long Zhang ,  Weifeng Sun ,  Siyang Liu ,  Chengwu Pan ,  Guiqiang Zheng ,  Longxing Shi

IPC: H01L27/06 ,  H01L23/528 ,  H01L29/20 ,  H01L29/778 ,  H01L29/8605 ,  H01L29/872 ,  H01L49/02 ,  H02M1/08

CPC classification number: H01L27/0605 ,  H01L23/5286 ,  H01L27/0629 ,  H01L27/0635 ,  H01L28/60 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/8605 ,  H01L29/872 ,  H02M1/08

Abstract: In the monolithically integrated GaN-based half-bridge circuit, a nucleation layer, a buffer layer, a channel layer and a barrier layer are sequentially provided on a conductive substrate, the barrier layer and the channel layer are separated by isolation layers, and a diode, an integrated capacitor, a low-side transistor, a high-side transistor, a first integrated resistor and a second integrated resistor are provided. The half-bridge circuit includes: a low-side transistor and a high-side transistor, wherein a drain of the low-side transistor is connected to a source of the high-side transistor and also connected to an output terminal Vout, and a substrate of the low-side transistor is connected to a substrate of the high-side transistor, wherein a series resistor is connected in parallel to a drain of the high-side transistor and a source of the low-side transistor.