公开(公告)号：US12119395B2

公开(公告)日：2024-10-15

申请号：US17762212

申请日：2020-08-26

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Long Zhang ,  Jie Ma ,  Yan Gu ,  Sen Zhang ,  Jing Zhu ,  Jinli Gong ,  Weifeng Sun ,  Longxing Shi

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7394 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/1095

Abstract: An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.

公开(公告)号：US11742423B2

公开(公告)日：2023-08-29

申请号：US17761510

申请日：2020-08-20

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jing Zhu ,  Guichuang Zhu ,  Nailong He ,  Sen Zhang ,  Shaohong Li ,  Weifeng Sun ,  Longxing Shi

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7824 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095

Abstract: A laterally double-diffused metal oxide semiconductor device is provided, including: a drift region (3) having a first conductivity type; a first body region (10) disposed on the drift region (3) and having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; a first conductivity type region (13) disposed in the first body region (10); a second body region (12) disposed in the first conductivity type region (13) and having the second conductivity type; a source region (11) disposed in the second body region (12) and having the first conductivity type; and a contact region (9) disposed in the first body region (10) and having the second conductivity type.

公开(公告)号：US10340906B2

公开(公告)日：2019-07-02

申请号：US15779432

申请日：2017-01-23

Applicant: SOUTHEAST UNIVERSITY ,  SOUTHEAST UNIVERSITY-WUXI INTEGRATED CIRCUIT TECHNOLOGY RESEARCH INSTITUTE

Inventor： Weifeng Sun ,  Yunwu Zhang ,  Kuo Yu ,  Jing Zhu ,  Shen Xu ,  Qinsong Qian ,  Siyang Liu ,  Shengli Lu ,  Longxing Shi

IPC: H02M3/07 ,  H03K17/06 ,  H03K17/16 ,  H03K17/687 ,  H03K19/0185 ,  H01L27/07 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10

Abstract: Parasitic high-voltage diodes implemented by integration technology in a high-voltage level shift circuit are used for charging a bootstrap capacitor CB, wherein a power supply end of the high voltage level shift circuit is a high-side floating power supply VB, and a reference ground is a floating voltage PGD that is controlled by a bootstrap control circuit. A first parasitic diode DB1 and a second parasitic diode DB2 are provided between the VB and the PGD. The bootstrap control circuit is controlled by a high-side signal and a low-side signal.

公开(公告)号：US11152936B2

公开(公告)日：2021-10-19

申请号：US17044623

申请日：2020-04-15

Applicant: SOUTHEAST UNIVERSITY

Inventor： Jing Zhu ,  Weifeng Sun ,  Bowei Yang ,  Siyuan Yu ,  Yangyang Lu ,  Longxing Shi

IPC: H03K3/00 ,  H03K17/08 ,  H03K17/16 ,  H03K17/687 ,  H03K19/20

Abstract: The present invention discloses a gate drive circuit for reducing a reverse recovery current of a power device, and belongs to the field of basic electronic circuit technologies. The gate drive circuit includes a high-voltage LDMOS transistor, a diode forming a freewheeling path when the diode is turned on or a low-voltage MOS transistor in anti-parallel connection with a body diode, and a voltage detection circuit. When the power device is turned off, a freewheeling current produced by an inductive load flows through a freewheeling diode, the voltage detection circuit detects that the freewheeling diode is turned on, and an output signal is processed by a control circuit, to cause the drive circuit to output a high level, so that channels of the power device and the high-voltage LDMOS transistor are turned on, the freewheeling current flows through the conductive channels, almost not through the freewheeling diode, and there is no reverse recovery current in the freewheeling diode at this time, thereby reducing the reverse recovery current of the power device.

公开(公告)号：US20140306266A1

公开(公告)日：2014-10-16

申请号：US14349632

申请日：2012-10-24

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Siyang Liu ,  Jing Zhu ,  Qinsong Qian ,  Shen Xu ,  Shengli Lu ,  Longxing Shi

IPC: H01L29/739 ,  H01L27/12 ,  H01L27/06

CPC classification number: H01L29/7394 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0638 ,  H01L29/404

Abstract: A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.

Abstract translation: 一种高电流，N型绝缘体上的横向绝缘栅双极晶体管，包括：P型衬底，设置在P型衬底上的掩埋氧化物层，设置在P型衬底上的N型外延层 氧化物层和N型缓冲阱捕获区。 P型体区域和N型中央缓冲区捕获区域设置在N型外延层内部; P型漏极区域设置在缓冲陷阱区域中; N型源极区域和P型体接触区域设置在P型体区域中; N型基极区域和P型发射极区域设置在缓冲陷阱区域中; 栅极和场氧化物层设置在N型外延层上; 多晶硅栅极设置在栅极氧化物层上; 并且钝化层和金属层设置在对称晶体管的表面上。 改善P型发射极区域的输出和电流密度，而不增加晶体管的面积。

公开(公告)号：US09159818B2

公开(公告)日：2015-10-13

申请号：US14349632

申请日：2012-10-24

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Siyang Liu ,  Jing Zhu ,  Qinsong Qian ,  Shen Xu ,  Shengli Lu ,  Longxing Shi

IPC: H01L27/24 ,  H01L29/739 ,  H01L29/40 ,  H01L27/12 ,  H01L29/06 ,  H01L27/06

CPC classification number: H01L29/7394 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0638 ,  H01L29/404

Abstract: A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.

Abstract translation: 一种高电流，N型绝缘体上的横向绝缘栅双极晶体管，包括：P型衬底，设置在P型衬底上的掩埋氧化物层，设置在P型衬底上的N型外延层 氧化物层和N型缓冲阱捕获区。 P型体区域和N型中央缓冲区捕获区域设置在N型外延层内部; P型漏极区域设置在缓冲陷阱区域中; N型源极区域和P型体接触区域设置在P型体区域中; N型基极区域和P型发射极区域设置在缓冲陷阱区域中; 栅极和场氧化物层设置在N型外延层上; 多晶硅栅极设置在栅极氧化物层上; 并且钝化层和金属层设置在对称晶体管的表面上。 改善P型发射极区域的输出和电流密度，而不增加晶体管的面积。

公开(公告)号：US20140203406A1

公开(公告)日：2014-07-24

申请号：US14240287

申请日：2012-08-14

Applicant: SOUTHEAST UNIVERSITY

Inventor： Longxing Shi ,  Qinsong Qian ,  Weifeng Sun ,  Jing Zhu ,  Xianguo Huang ,  Shengli Lu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/761

CPC classification number: H01L29/0646 ,  H01L21/265 ,  H01L21/761 ,  H01L21/823481 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/7835

Abstract: An isolation structure of a high-voltage driving circuit includes a P-type substrate and a P-type epitaxial layer; a high voltage area, a low voltage area and a high and low voltage junction terminal area are arranged on the P-type epitaxial layer; a first P-type junction isolation area is arranged between the high and low voltage junction terminal area and the low voltage area, and a high-voltage insulated gate field effect tube is arranged between the high voltage area and the low voltage area; two sides of the high-voltage insulated gate field effect tube and an isolation structure between the high-voltage insulated gate field effect tube and a high side area are formed as a second P-type junction isolation area.

Abstract translation: 高电压驱动电路的隔离结构包括P型衬底和P型外延层; 在P型外延层上布置有高电压区域，低电压区域和高低压端子区域; 在高低压区和低电压区之间设置第一P型结隔离区，高电压区与低压区之间设置高压绝缘栅场效应管; 高压绝缘栅场效应管的两侧和高压绝缘栅场效应管与高边区之间的隔离结构形成为第二P型结隔离区。

公开(公告)号：US09240469B2

公开(公告)日：2016-01-19

申请号：US14439715

申请日：2012-12-27

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Jing Zhu ,  Shen Xu ,  Qinsong Qian ,  Siyang Liu ,  Shengli Lu ,  Longxing Shi

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/49 ,  H01L29/10 ,  H01L29/08 ,  H01L23/528

CPC classification number: H01L29/7394 ,  H01L23/528 ,  H01L29/0611 ,  H01L29/0696 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/1008 ,  H01L29/4916 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region. The present invention greatly increases current density of a transverse ultra-thin insulated gate bipolar transistor, thus significantly improving the performance of an intelligent power module.

Abstract translation: 具有电流密度的横向超薄绝缘栅双极晶体管包括：P基板，其中P基板在其上设置有掩埋氧化物层，所述掩埋氧化物层在其上设置有N外延层，提供N外延层 在其中具有N阱区域和P基极区域，P基极区域中设置有第一P接触区域和N源极区域，N阱区域中设置有N个缓冲区域，N阱区域设置有 在其上的场氧化物层，N缓冲区在其中设置有P漏极区，N外延层中设置有包括P环状基极区的P基区阵列，P基区阵列位于N阱之间 区域和P基区域中，P环状基部区域设置有第二P接触区域和N环状源极区域，第二P接触区域位于N环状源极区域中。 本发明大大增加了横向超薄绝缘栅双极晶体管的电流密度，从而显着提高了智能功率模块的性能。

公开(公告)号：US20150270377A1

公开(公告)日：2015-09-24

申请号：US14439715

申请日：2012-12-27

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Jing Zhu ,  Shen Xu ,  Qinsong Qian ,  Siyang Liu ,  Shengli Lu ,  Longxing Shi

IPC: H01L29/739 ,  H01L23/528 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L29/7394 ,  H01L23/528 ,  H01L29/0611 ,  H01L29/0696 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/1008 ,  H01L29/4916 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region. The present invention greatly increases current density of a transverse ultra-thin insulated gate bipolar transistor, thus significantly improving the performance of an intelligent power module.

Abstract translation: 具有电流密度的横向超薄绝缘栅双极晶体管包括：P基板，其中P基板在其上设置有掩埋氧化物层，所述掩埋氧化物层在其上设置有N外延层，提供N外延层 在其中具有N阱区域和P基极区域，P基极区域中设置有第一P接触区域和N源极区域，N阱区域中设置有N个缓冲区域，N阱区域设置有 在其上的场氧化物层，N缓冲区在其中设置有P漏极区，N外延层中设置有包括P环状基极区的P基区阵列，P基区阵列位于N阱之间 区域和P基区域中，P环状基部区域设置有第二P接触区域和N环状源极区域，第二P接触区域位于N环状源极区域中。 本发明大大增加了横向超薄绝缘栅双极晶体管的电流密度，从而显着提高了智能功率模块的性能。

公开(公告)号：US11367785B2

公开(公告)日：2022-06-21

申请号：US17606216

申请日：2020-03-31

Applicant: SOUTHEAST UNIVERSITY

Inventor： Jing Zhu ,  Ankang Li ,  Long Zhang ,  Weifeng Sun ,  Shengli Lu ,  Longxing Shi

IPC: H01L29/73 ,  H01L29/739 ,  H01L29/10

Abstract: A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer. The polysilicon gate includes a first gate located above the surface of the P-type body region and a second gate located above the pinch-off region and the N-type drift region. The first gate is connected to a first gate resistor, and the second gate is connected to a second gate resistor.