公开(公告)号：US20240405798A1

公开(公告)日：2024-12-05

申请号：US18651120

申请日：2024-04-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Riccardo CONDORELLI ,  Antonino MONDELLO ,  Michele Alessandro CARRANO ,  Salvatore COSTA ,  Michele BOTTARO ,  Pascal FABRE ,  Philippe BOLLARD ,  Felice Alberto TORRISI

IPC: H04B1/7183 ,  H04L7/033

Abstract: Method of operating a radio communication system during a stand-by time interval in a stand-by state. The method comprises: applying clock division processing to a reference clock signal and producing a divided clock signal; applying PLL processing to the divided clock signal producing a PLL clock signal; receiving at least one input signal; when the input signal has a first logic value, interrupting applying PLL processing to the divided clock signal and enabling counting clock signal edges of the divided clock signal; when said counting clock signal edges reaches a first target count value, restarting applying PLL processing; continuing counting clock signal edges until reaching a second target count value; when said counting reaches the second target count value, issuing and sampling an end-count signal based on the PLL clock signal, producing a timing clock signal as a result and providing the timing clock signal to a user circuit.

公开(公告)号：US20240242749A1

公开(公告)日：2024-07-18

申请号：US18410049

申请日：2024-01-11

Applicant: STMicroelectronics International N.V.

Inventor： Riccardo CONDORELLI ,  Antonino MONDELLO ,  Michele Alessandro CARRANO ,  Michele BOTTARO ,  Salvatore COSTA ,  Jacques TALAYSSAT

IPC: G11C7/24 ,  G11C7/20

CPC classification number: G11C7/24 ,  G11C7/20

Abstract: A reset pad circuit has first and second inputs coupled, respectively, to a first reset access port receiving a first reset request and a second reset access port. The reset pad circuit generates a first reset state signal. An internal reset activation gate has inputs coupled to internal resources and an output that applies a reset request to the second reset access port. A memory element has first and second inputs coupled, respectively, to the output of the reset activation gate and the output of the reset pad circuit. The memory element generates a second reset state signal when receiving the reset request until receiving the first reset state signal. A reset forward gate coupled to outputs of the reset pad circuit and the memory element generates a system reset request in response to the first reset state signal or the second state signal.