公开(公告)号：US20030223298A1

公开(公告)日：2003-12-04

申请号：US10377297

申请日：2003-02-28

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Ankur Bal ,  Manish Agarwal

IPC: G11C007/00

CPC classification number: H03K19/17776 ,  G11C7/20 ,  H03K19/1776 ,  H03K19/17772 ,  H03K19/1778

Abstract: An efficient method and electronic circuit for initializing latch arrays in an electronic device including an FPGA and a memory device comprising a group of one or more data latches, each comprising a pair of cross-coupled inverting logic elements, characterized in that it includes a means for simultaneously initializing each data latch to a predetermined logic state, without requiring any additional circuit elements with any data latch for this purpose.

Abstract translation: 一种用于在包括FPGA的电子设备中初始化锁存器阵列的有效方法和电子电路，以及包括一组一个或多个数据锁存器的存储器件，每个数据锁存器包括一对交叉耦合的反相逻辑元件，其特征在于， 用于同时将每个数据锁存器初始化为预定的逻辑状态，而不需要任何额外的电路元件与任何数据锁存器用于此目的。

公开(公告)号：US20040178821A1

公开(公告)日：2004-09-16

申请号：US10739395

申请日：2003-12-18

Applicant: STMICROELECTRONICS PVT. LTD.

Inventor： Ankur Bal ,  Namerita Khanna

IPC: H03K019/177

CPC classification number: H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

Abstract: This invention relates to a high performance interconnect architecture providing reduced delay minimized electro-migration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.

Abstract translation: 本发明涉及一种高性能互连架构，其提供减少的延迟最小化的电迁移和FPGA中的减少的区域，包括由互连的逻辑块组成的多个瓦片，其由中间的逻辑块分隔。 每组相互连接的逻辑块由互连段链接，该互连段通过互连层在中间逻辑块上以直线路由，并且通过连接段选择性地连接到每端的逻辑块。

公开(公告)号：US20040036499A1

公开(公告)日：2004-02-26

申请号：US10464420

申请日：2003-06-17

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Ankur Bal

IPC: H03K019/173

CPC classification number: H03K19/17736 ,  H03K19/17796

Abstract: An FPCA includes a scheme for peripheral routing that provides symmetrical routing across its entire area including the periphery by incorporating peripheral routing lines of equal length that are symmetrically deflected orthogonally. The symmetrical peripheral routing lines are connected to switch boxes and connection boxes at the periphery for maintaining constant routing channel width.

Abstract translation: FPCA包括用于外围路由的方​​案，其通过并入正交对称偏转的相等长度的外围路由线来提供包括外围在内的整个区域的对称路由。 对称的外围路由线路连接到外围的交换机和连接盒，以保持不断的路由信道宽度。