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    Method and apparatus of reloading erroneous configuration data frames during configuration of programmable logic devices
    1.
    发明申请
    Method and apparatus of reloading erroneous configuration data frames during configuration of programmable logic devices 失效
    在配置可编程逻辑器件期间重新加载错误配置数据帧的方法和装置

    公开(公告)号：US20040153923A1

    公开(公告)日：2004-08-05

    申请号：US10667199

    申请日：2003-09-18

    Applicant: STMicroelectronics Pvt, Ltd.

    Inventor： Ashish Kumar Goel ,  Namerita Khanna ,  Davinder Aggarwal

    IPC: G01R031/28

    CPC classification number: G06F11/1402 ,  G01R31/318519 ,  G06F11/1008

    Abstract: An improved method and apparatus for reloading frames in which errors are detected during the Programmable Logic Device configuration. A configuration data frame for a FPGA is loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An error counter value is maintained by the apparatus and is incremented each time an error with a frame is detected. The incremented value is compared by a Comparator circuit with a pre-determined threshold value nullnnull. If a match is found then the configuration process is aborted, else the data frame is reloaded in the configuration memory, transferred again to the frame register and rechecked for errors. If no error is detected with the reloaded frame, the error counter value is reset and the next frame is loaded until the FPGA configuration process is over.

    Abstract translation: 一种用于重新加载在可编程逻辑器件配置期间检测到错误的帧的改进的方法和装置。 FPGA的配置数据帧被加载到FPGA的帧寄存器，并且还加载到检测错误的错误检测电路。 错误计数器值由设备维护，并且每当检测到帧的错误时递增。 递增值由具有预定阈值“n”的比较器电路进行比较。 如果发现匹配，则配置过程将中止，否则数据帧将重新加载到配置存储器中，再次传输到帧寄存器并重新检查错误。 如果在重新加载的帧中没有检测到错误，错误计数器值将被复位，下一个帧被加载，直到FPGA配置过程结束。

    Low power clock distribution scheme
    2.
    发明申请
    Low power clock distribution scheme 有权
    低功率时钟分配方案

    公开(公告)号：US20030218480A1

    公开(公告)日：2003-11-27

    申请号：US10407801

    申请日：2003-04-04

    Applicant: Indian ST (STMicroelectronics Pvt. Ltd.)

    Inventor： Parvesh Swami ,  Namerita Khanna ,  Deepak Agarwal

    IPC: H03K019/173

    CPC classification number: H03K19/1774 ,  H03K19/17784

    Abstract: An electronic circuit containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation. The electronic circuit includes an improved clock distribution scheme that reduces power consumption, comprising identifying means for determining the select/deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.

    Abstract translation: 一种包含一个或多个数字同步顺序逻辑块的电子电路，其中至少一个在操作期间被选择或取消选择。 电子电路包括一种降低功耗的改进的时钟分配方案，包括识别装置，用于确定每个所述可取消同步顺序逻辑块的选择/取消选择状态，耦合到禁用装置，用于禁止每个取消选择的同步顺序逻辑块的时钟输入。

    High performance interconnect architecture for field programmable gate arrays
    3.
    发明申请
    High performance interconnect architecture for field programmable gate arrays 有权
    用于现场可编程门阵列的高性能互连架构

    公开(公告)号：US20040178821A1

    公开(公告)日：2004-09-16

    申请号：US10739395

    申请日：2003-12-18

    Applicant: STMICROELECTRONICS PVT. LTD.

    Inventor： Ankur Bal ,  Namerita Khanna

    IPC: H03K019/177

    CPC classification number: H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

    Abstract: This invention relates to a high performance interconnect architecture providing reduced delay minimized electro-migration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.

    Abstract translation: 本发明涉及一种高性能互连架构，其提供减少的延迟最小化的电迁移和FPGA中的减少的区域，包括由互连的逻辑块组成的多个瓦片，其由中间的逻辑块分隔。 每组相互连接的逻辑块由互连段链接，该互连段通过互连层在中间逻辑块上以直线路由，并且通过连接段选择性地连接到每端的逻辑块。

    Architecture for programmable logic device
    5.
    发明申请
    Architecture for programmable logic device 有权
    可编程逻辑器件的架构

    公开(公告)号：US20030214321A1

    公开(公告)日：2003-11-20

    申请号：US10407802

    申请日：2003-04-04

    Applicant: STMicroelectronics Pvt. Ltd.

    Inventor： Parvesh Swami ,  Namerita Khanna ,  Deepak Agarwal

    IPC: H03K019/173

    CPC classification number: H03K19/17736

    Abstract: An improved Programmable Logic Device architecture that provides more efficient utilization of resources by enabling access to defined circuit elements in the domain of any Programmable Logic Block (PLB) from any other PLB in the device, by incorporating a connecting means in the routing structure for selectively connecting the input or output of the circuit element in the domain of the PLB to the common interconnect matrix connecting all the PLBs together.

    Abstract translation: 一种改进的可编程逻辑设备架构，其通过在设备中的任何其他PLB上访问任何可编程逻辑块（PLB）的域中的定义的电路元件来提供资源的更有效的利用，通过在路由结构中并入选择性地连接 将PLB域中的电路元件的输入或输出连接到将所有PLB连接在一起的公共互连矩阵。

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