公开(公告)号：US20040017702A1

公开(公告)日：2004-01-29

申请号：US10453466

申请日：2003-06-03

Applicant: STMICROELECTRONICS S.A.

Inventor： Richard Fournel ,  Jean-Pierre Schoellkopf ,  Philippe Candelier

IPC: G11C029/00

CPC classification number: G11C8/12 ,  G11C16/08

Abstract: A few times programmable (FTP) storage element is provided. The FTP storage element includes a set of N elementary memory units and multiple selection circuits. Each of the elementary memory units includes an address bus for connection to a main address bus and a data bus for connection to a main data bus. The selection circuits generate successive selection signals for successively selecting one of the elementary memory units in order to give exclusive access to the one selected elementary memory unit. The selection circuits operate so as to automatically select a next one of the elementary memory units upon detection of a predetermined condition. In preferred embodiments, each of the elementary memory units is programmable.

Abstract translation: 提供了几次可编程（FTP）存储元件。 FTP存储元件包括一组N个基本存储器单元和多个选择电路。 每个基本存储器单元包括用于连接到主地址总线的地址总线和用于连接到主数据总线的数据总线。 选择电路产生连续的选择信号，用于连续选择一个基本存储器单元，以给予对所选择的一个基本存储单元的独占访问。 选择电路工作，以便在检测到预定条件时自动选择下一个基本存储器单元。 在优选实施例中，每个基本存储器单元是可编程的。

公开(公告)号：US20040217305A1

公开(公告)日：2004-11-04

申请号：US10778323

申请日：2004-02-13

Applicant: STMicroelectronics S.A.

Inventor： Jean-Pierre Schoellkopf ,  Herve Jaouen

IPC: G21G005/00

CPC classification number: H01L21/76807 ,  H01L21/76801 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of repairing a defect in an integrated electronic circuit caused by an incorrect lithographic mask includes the formation of an electrical isolation between two conducting parts of the circuit. The electrical isolation is obtained by at least partly filling, with an electrically insulating material, a volume hollowed out beforehand which would otherwise, and incorrectly, form an electrical connection between the two conducting parts. To do this, a mask having an aperture revealing the hollowed out volume is formed on the circuit, and the mask used to direct the filling of the electrically insulating material and correction of the lithography defined defect.

Abstract translation: 修复由不正确的光刻掩模引起的集成电子电路中的缺陷的方法包括在电路的两个导电部分之间形成电隔离。 电隔离是通过用电绝缘材料至少部分地填充预先挖空的体积获得的，否则并且不正确地在两个导电部件之间形成电连接。 为此，在电路上形成具有露出掏空体积的孔径的掩模，以及用于引导电绝缘材料的填充的掩模和校正光刻限定的缺陷。

公开(公告)号：US20040044943A1

公开(公告)日：2004-03-04

申请号：US10453844

申请日：2003-06-03

Applicant: STMICROELECTRONICS S.A.

Inventor： Francois Jacquet ,  Jean-Pierre Schoellkopf

IPC: G11C029/00

CPC classification number: G06F11/1008 ,  G06F11/1048

Abstract: A memory circuit with an error correcting system comprising an address bus (102), an input data bus (108), and an output data bus (115), the circuit comprising a memory having an address bus (113), a data bus (114) and an error correcting circuit comprising an encoder (107). A first address register (104) is connected to the input address bus of the circuit for successively storing addresses corresponding to memory write operations only. A second data register (105) is connected to the input data bus of the circuit (108) for storing data transmitted to the encoder (107). Circuits make it possible to introduce a one-cycle shift into the memory writes, without modifying reads, giving the encoder more time to compute error correcting codes.

Abstract translation: 一种具有包括地址总线（102），输入数据总线（108）和输出数据总线（115）的纠错系统的存储器电路，该电路包括具有地址总线（113），数据总线 114）和包括编码器（107）的纠错电路。 第一地址寄存器（104）连接到电路的输入地址总线，用于仅依次存储对应于存储器写入操作的地址。 第二数据寄存器（105）连接到电路（108）的输入数据总线，用于存储发送到编码器（107）的数据。 电路使得可以在存储器写入中引入一个周期的移位，而不修改读取，给编码器更多的时间来计算纠错码。