公开(公告)号：US20040017702A1

公开(公告)日：2004-01-29

申请号：US10453466

申请日：2003-06-03

Applicant: STMICROELECTRONICS S.A.

Inventor： Richard Fournel ,  Jean-Pierre Schoellkopf ,  Philippe Candelier

IPC: G11C029/00

CPC classification number: G11C8/12 ,  G11C16/08

Abstract: A few times programmable (FTP) storage element is provided. The FTP storage element includes a set of N elementary memory units and multiple selection circuits. Each of the elementary memory units includes an address bus for connection to a main address bus and a data bus for connection to a main data bus. The selection circuits generate successive selection signals for successively selecting one of the elementary memory units in order to give exclusive access to the one selected elementary memory unit. The selection circuits operate so as to automatically select a next one of the elementary memory units upon detection of a predetermined condition. In preferred embodiments, each of the elementary memory units is programmable.

Abstract translation: 提供了几次可编程（FTP）存储元件。 FTP存储元件包括一组N个基本存储器单元和多个选择电路。 每个基本存储器单元包括用于连接到主地址总线的地址总线和用于连接到主数据总线的数据总线。 选择电路产生连续的选择信号，用于连续选择一个基本存储器单元，以给予对所选择的一个基本存储单元的独占访问。 选择电路工作，以便在检测到预定条件时自动选择下一个基本存储器单元。 在优选实施例中，每个基本存储器单元是可编程的。

公开(公告)号：US20040252554A1

公开(公告)日：2004-12-16

申请号：US10726263

申请日：2003-12-02

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel ,  Emmanuel Vincent ,  Sylvie Bruyere ,  Philippe Candelier ,  Francois Jacquet

IPC: G11C016/04

CPC classification number: G11C14/00 ,  G11C17/14

Abstract: An SRAM memory cell includes first and second inverters (14, 16) interconnected between first and second data nodes. Each inverter is formed from complementary MOS transistors (18, 20, 18null, 20null) connected in series between a DC voltage supply source and a grounding circuit (22). A circuit (28, 30) programs the MOS transistors by causing an irreversible degradation of a gate oxide layer of at least some of the transistors (18, 18null).

Abstract translation: SRAM存储单元包括在第一和第二数据节点之间互连的第一和第二反相器（14,16）。 每个反相器由串联连接在DC电压源和接地电路（22）之间的互补MOS晶体管（18,20,18'，20'）形成。 电路（28,30）通过使至少一些晶体管（18,18'）的栅极氧化层不可逆地退化来对MOS晶体管进行编程。