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公开(公告)号:US10483220B2
公开(公告)日:2019-11-19
申请号:US15239545
申请日:2016-08-17
Applicant: STMICROELECTRONICS S.R.L.
Inventor: Andrea Paleari , Antonella Milani , Lucrezia Guarino , Federica Ronchi
IPC: H01L23/00 , H01L21/768 , H01L23/525 , H01L23/528 , H01L23/532
Abstract: In one embodiment, a method manufactures a semiconductor device including metallizations having peripheral portions with one or more underlying layers having marginal regions extending facing the peripheral portions. The method includes: providing a sacrificial layer to cover the marginal regions of the underlying layer, providing the metallizations while the marginal regions of the underlying layer are covered by the sacrificial layer, and removing the sacrificial layer so that the marginal regions of the underlying layer extend facing the peripheral portions in the absence of contact interface therebetween, thereby avoiding thermo-mechanical stresses.
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公开(公告)号:US20170221840A1
公开(公告)日:2017-08-03
申请号:US15239545
申请日:2016-08-17
Applicant: STMICROELECTRONICS S.R.L.
Inventor: Andrea Paleari , Antonella Milani , Lucrezia Guarino , Federica Ronchi
IPC: H01L23/00
Abstract: In one embodiment, a method manufactures a semiconductor device including metallizations having peripheral portions with one or more underlying layers having marginal regions extending facing the peripheral portions. The method includes: providing a sacrificial layer to cover the marginal regions of the underlying layer, providing the metallizations while the marginal regions of the underlying layer are covered by the sacrificial layer, and removing the sacrificial layer so that the marginal regions of the underlying layer extend facing the peripheral portions in the absence of contact interface therebetween, thereby avoiding thermo-mechanical stresses.
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3.
公开(公告)号:US09960131B2
公开(公告)日:2018-05-01
申请号:US15251355
申请日:2016-08-30
Applicant: STMICROELECTRONICS S.R.L.
Inventor: Paolo Colpani , Antonella Milani , Lucrezia Guarino , Andrea Paleari
CPC classification number: H01L24/05 , H01L23/3192 , H01L23/50 , H01L23/522 , H01L23/562 , H01L24/00 , H01L24/03 , H01L2224/02205 , H01L2224/02215 , H01L2224/04042 , H01L2224/05018 , H01L2224/05025 , H01L2224/05082 , H01L2224/05147 , H01L2224/05562 , H01L2224/05655 , H01L2924/04642 , H01L2924/05042 , H01L2924/351
Abstract: In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a “dummy” via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10−6 m.) and approximately 10 micron (10−5 m.) from each one of said converging sides landing on an underlying metal layer.
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4.
公开(公告)号:US20170221841A1
公开(公告)日:2017-08-03
申请号:US15251355
申请日:2016-08-30
Applicant: STMICROELECTRONICS S.R.L.
Inventor: Paolo Colpani , Antonella Milani , Lucrezia Guarino , Andrea Paleari
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L23/3192 , H01L23/50 , H01L23/522 , H01L23/562 , H01L24/00 , H01L24/03 , H01L2224/02205 , H01L2224/02215 , H01L2224/04042 , H01L2224/05018 , H01L2224/05025 , H01L2224/05082 , H01L2224/05147 , H01L2224/05562 , H01L2224/05655 , H01L2924/04642 , H01L2924/05042 , H01L2924/351
Abstract: In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a “dummy” via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10−6 m.) and approximately 10 micron (10−5 m.) from each one of said converging sides landing on an underlying metal layer.
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