公开(公告)号：US12057474B2

公开(公告)日：2024-08-06

申请号：US17325932

申请日：2021-05-20

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Antonino Schillaci ,  Paola Maria Ponzio ,  Roberto Cammarata

IPC: H03F3/195 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H03F3/217

CPC classification number: H01L29/0634 ,  H01L29/66712 ,  H01L29/7811 ,  H03F3/2176 ,  H03F2200/451

Abstract: A semiconductor MOS device having an epitaxial layer with a first conductivity type formed by a drain region and by a drift region. The drift region accommodates a plurality of first columns with a second conductivity type and a plurality of second columns with the first conductivity type, the first and second columns alternating with each other and extending on the drain region. Insulated gate regions are each arranged on top of a respective second column; body regions having the second conductivity type extend above and at a distance from a respective first column, thus improving the output capacitance Cds of the device, for use in high efficiency RF applications.

公开(公告)号：US09899508B1

公开(公告)日：2018-02-20

申请号：US15289828

申请日：2016-10-10

Applicant: STMicroelectronics S.r.l.

Inventor： Antonino Schillaci ,  Paola Maria Ponzio ,  Alessandro Angelo Alfio Palazzo

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7802 ,  H01L21/265 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/66545 ,  H01L29/66712

Abstract: Embodiments are directed to super-junction semiconductor devices having an inactive region positioned between active cells. In one embodiment, a semiconductor device is provided that includes a substrate and a drain region on the substrate. The drain region has a first conductivity type. A plurality of first columns is disposed on the drain region, with the first columns having the first conductivity type. A plurality of second columns is disposed on the drain region, with the second columns having a second conductivity type. The first and second columns are alternately arranged such that each of the second columns is positioned between respective first columns. First and second gate structures are included that overlie respective first columns, and a body region is included that has the second conductivity type. The body region abuts at least two second columns and at least one first column positioned between the at least two second columns.

公开(公告)号：US09508846B2

公开(公告)日：2016-11-29

申请号：US14662652

申请日：2015-03-19

Applicant: STMicroelectronics S.r.l.

Inventor： Antonino Schillaci ,  Alfonso Patti ,  Paola Maria Ponzio

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7831

Abstract: A MOS semiconductor device of a vertical type has: a functional layer, having a first type of conductivity; gate structures, which are formed above the functional layer and have a region of dielectric material and an electrode region; body wells, which have a second type of conductivity, are formed within the functional layer, and are separated by a surface separation region; source regions, which have the first type of conductivity and are formed within the body wells. Each gate structure extends laterally above just one respective body well and does not overlap the surface separation region of the functional layer. The device may further have: at least one shield structure, arranged between adjacent gate structures above the surface separation region; and/or at least one doped control region, having the second type of conductivity, arranged within the surface separation region, which are both set at the source potential.

Abstract translation: 垂直型的MOS半导体器件具有：具有第一类导电性的功能层; 栅极结构，其形成在功能层上方并具有介电材料区域和电极区域; 具有第二类导电性的主体孔形成在功能层内，并被表面分离区分离; 源区，其具有第一类导电性并形成在体孔内。 每个栅极结构横向仅在一个相应的主体阱上方延伸，并且不与功能层的表面分离区域重叠。 该装置还可以具有：至少一个屏蔽结构，布置在表面分离区域上方的相邻门结构之间; 和/或具有第二类型导电性的至少一个掺杂控制区域，布置在表面分离区域内，两者都被设置在源极电位。

公开(公告)号：US11024707B2

公开(公告)日：2021-06-01

申请号：US16438286

申请日：2019-06-11

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Antonino Schillaci ,  Paola Maria Ponzio ,  Roberto Cammarata

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H03F3/217

Abstract: A semiconductor MOS device having an epitaxial layer with a first conductivity type formed by a drain region and by a drift region. The drift region accommodates a plurality of first columns with a second conductivity type and a plurality of second columns with the first conductivity type, the first and second columns alternating with each other and extending on the drain region. Insulated gate regions are each arranged on top of a respective second column; body regions having the second conductivity type extend above and at a distance from a respective first column, thus improving the output capacitance Cds of the device, for use in high efficiency RF applications.

公开(公告)号：US20150303300A1

公开(公告)日：2015-10-22

申请号：US14662652

申请日：2015-03-19

Applicant: STMicroelectronics S.r.l.

Inventor： Antonino Schillaci ,  Alfonso Patti ,  Paola Maria Ponzio

IPC: H01L29/78 ,  H01L29/40

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7831

Abstract: A MOS semiconductor device of a vertical type has: a functional layer, having a first type of conductivity; gate structures, which are formed above the functional layer and have a region of dielectric material and an electrode region; body wells, which have a second type of conductivity, are formed within the functional layer, and are separated by a surface separation region; source regions, which have the first type of conductivity and are formed within the body wells. Each gate structure extends laterally above just one respective body well and does not overlap the surface separation region of the functional layer. The device may further have: at least one shield structure, arranged between adjacent gate structures above the surface separation region; and/or at least one doped control region, having the second type of conductivity, arranged within the surface separation region, which are both set at the source potential.

Abstract translation: 垂直型的MOS半导体器件具有：具有第一类导电性的功能层; 栅极结构，其形成在功能层上方并具有介电材料区域和电极区域; 具有第二类导电性的主体孔形成在功能层内，并被表面分离区分离; 源区，其具有第一类导电性并形成在体孔内。 每个栅极结构横向仅在一个相应的主体阱上方延伸，并且不与功能层的表面分离区域重叠。 该装置还可以具有：至少一个屏蔽结构，布置在表面分离区域上方的相邻门结构之间; 和/或具有第二类型导电性的至少一个掺杂控制区域，布置在表面分离区域内，两者都被设置在源极电位。