公开(公告)号：US20230090664A1

公开(公告)日：2023-03-23

申请号：US17946298

申请日：2022-09-16

Applicant: STMicroelectronics S.r.l.

Inventor： Antonino MONDELLO ,  Michele Alessandro CARRANO ,  Riccardo CONDORELLI

IPC: G06F21/57 ,  G06F8/65 ,  G06F21/60

Abstract: The present disclosure relates to a method including executing, by an electronic device, a first firmware module stored in a volatile memory of the electronic device, the execution of the first firmware module causing an updated firmware key to be stored in a non-volatile memory of the electronic device, and uploading a second firmware module to the electronic device. The method also includes decrypting the second firmware module by a cryptographic processor of the electronic device based on the updated firmware key, and installing the decrypted second firmware module in the volatile memory of the electronic device at least partially overwriting the first firmware module.

公开(公告)号：US20160139287A1

公开(公告)日：2016-05-19

申请号：US14835935

申请日：2015-08-26

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Daniele MANGANO ,  Riccardo CONDORELLI

IPC: G01V3/10

CPC classification number: G01V3/10 ,  H03K17/9525

Abstract: A system for interfacing an LC sensor includes a starter configured to selectively start an oscillation of the LC sensor. The system also includes an analog peak detector configured to determine a signal (Vpeak) being indicative of a peak voltage of the oscillation of the LC sensor and a detector configured to determine a state of the LC sensor as a function of the signal (Vpeak) determined by the analog peak detector.

Abstract translation: 用于连接LC传感器的系统包括配置成选择性地启动LC传感器的振荡的起动器。 该系统还包括模拟峰值检测器，其被配置为确定指示LC传感器的振荡的峰值电压的信号（Vpeak）以及被配置为根据信号（Vpeak）确定LC传感器的状态的检测器， 由模拟峰值检测器确定。

公开(公告)号：US20230213578A1

公开(公告)日：2023-07-06

申请号：US18089764

申请日：2022-12-28

Applicant: STMicroelectronics S.r.l.

Inventor： Riccardo CONDORELLI ,  Antonino MONDELLO ,  Michele Alessandro CARRANO

IPC: G01R31/317 ,  G01R31/3173

CPC classification number: G01R31/31703 ,  G01R31/31725 ,  G01R31/3173

Abstract: A system-on-chip includes a process-voltage-temperature (PVT) sensor with a filter circuit that initiates a patterned digital signal and propagates the patterned digital signal in a manner responsive to variations in semiconductor material, operating supply voltage and operating temperature of the system-on-chip. A digital comparison circuit compares the initiated patterned digital signal and the propagated patterned digital signal. A warning signal is generated in response to the comparison where there is a detection of discrepancy between the initiated patterned digital signal and the propagated patterned digital signal.

公开(公告)号：US20190018051A1

公开(公告)日：2019-01-17

申请号：US16136121

申请日：2018-09-19

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Riccardo CONDORELLI ,  Daniele MANGANO

IPC: G01R27/26 ,  H03K17/95 ,  G01D5/20

Abstract: In one embodiment, an inductive/LC sensor device includes: an energy storage device for accumulating excitation energy, an LC sensor configured to oscillate using energy accumulated in the energy storage device and transferred to the LC sensor, an energy detector for detecting the energy accumulated in the energy storage device reaching a charge threshold, and at least one switch coupled with the energy detector for terminating accumulating excitation energy in the energy storage device when the charge threshold is detected having been reached by the energy detector.

公开(公告)号：US20200278711A1

公开(公告)日：2020-09-03

申请号：US16803942

申请日：2020-02-27

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Mirko DONDINI ,  Daniele MANGANO ,  Riccardo CONDORELLI

IPC: G05F1/575 ,  G06F1/10 ,  G06F13/40 ,  G05B19/042 ,  H03K19/17736 ,  H03B5/32

Abstract: An integrated circuit includes a clock control circuit coupled to a reference clock signal node and a plurality of circuits including a voltage regulator, a digital circuit, and an analog circuit. The voltage regulator, in operation, supplies a regulated voltage. The clock control circuit, in operation, generates a system clock. Input/output interface circuitry is coupled to the plurality of circuits and a common input/output node. The input/output interface circuitry, in operation, selectively couples one of the plurality of circuits to the common input/output node.

公开(公告)号：US20160352337A1

公开(公告)日：2016-12-01

申请号：US14971150

申请日：2015-12-16

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Salvatore Marco ROSSELLI ,  Daniele MANGANO ,  Riccardo CONDORELLI

IPC: H03K19/177 ,  H03K19/00

CPC classification number: H03K19/0008 ,  G06F15/7867 ,  G06F2209/507 ,  H03K19/1737 ,  H03K19/1776

Abstract: A circuit includes combinational circuit and sequential circuit elements coupled thereto. The circuit includes a multiplexor coupled to the combinational and sequential circuit elements, and a system register is coupled to the multiplexor. At least one portion of the combinational and sequential circuit elements is configured to selectively switch to operate as a random access memory.

Abstract translation: 电路包括组合电路和与其耦合的顺序电路元件。 电路包括耦合到组合和顺序电路元件的多路复用器，并且系统寄存器耦合到多路复用器。 组合和顺序电路元件的至少一部分被配置为选择性地切换为作为随机存取存储器操作。

公开(公告)号：US20160246324A1

公开(公告)日：2016-08-25

申请号：US14965002

申请日：2015-12-10

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Daniele MANGANO ,  Riccardo CONDORELLI

IPC: G06F1/12 ,  G06F1/14

CPC classification number: G06F1/12 ,  G06F1/14 ,  G06F1/3243 ,  H03L1/00 ,  Y02D10/152

Abstract: A clock generator includes a microcontroller unit calibrated by aligning at subsequent calibration times a frequency of a first clock with respect to the frequency of a second clock having a higher frequency accuracy than the first clock, with the frequency of the first clock varying between subsequent calibration times. The frequency of the first clock is aligned to a frequency which is offset by a certain amount with respect to the frequency of the second clock to counter frequency error which may accumulate over time due to the variation in the frequency of the first clock.

Abstract translation: 时钟发生器包括微处理器单元，该单元通过在随后的校准时间对准第一时钟的频率而相对于具有比第一时钟更高的频率精度的第二时钟的频率进行校准，第一时钟的频率在随后的校准之间变化 次 第一时钟的频率对应于相对于第二时钟的频率偏移一定量的频率，以对应于由于第一时钟的频率变化而随时间累积的对频率误差。