公开(公告)号：US20040068500A1

公开(公告)日：2004-04-08

申请号：US10267402

申请日：2002-10-08

Applicant: STMicroelectronics, Inc.

Inventor： Davide Rizzo ,  Osvaldo Colavin

IPC: G06F017/30

CPC classification number: G06F17/30985 ,  G06F7/026 ,  G06F7/24 ,  G06F2207/226

Abstract: A data sorting apparatus comprising 1) a storage sorter that sorts a data set according to a defined criteria; and 2) a query mechanism that receives intermediate sorted data values from the storage sorter and compares the intermediate sorted data values to at least one key value. The storage sorter comprises a priority queue for sorting the data set, wherein the priority queue comprises M processing elements. The query mechanism receives the intermediate sorted data values from the M processing elements. The query mechanism comprises a plurality of comparison circuits, each of the comparison circuits capable of detecting if one of the intermediate sorted data values is equal to the at least one key value or, if no match exists, extracting the minimal value greater than (or less than according to a defined criteria) the at least one key value.

Abstract translation: 一种数据分类装置，包括：1）根据所定义的标准对数据集排序的存储分类器; 以及2）查询机制，其从所述存储分类器接收中间排序数据值，并将所述中间排序数据值与至少一个键值进行比较。 存储分类器包括用于对数据集进行排序的优先级队列，其中优先级队列包括M个处理元素。 查询机制从M个处理单元接收中间排序数据值。 查询机制包括多个比较电路，每个比较电路能够检测中间分类数据值之一是否等于至少一个键值，或者如果不存在匹配，则提取大于（或 小于根据定义的标准）至少一个键值。

公开(公告)号：US20020180743A1

公开(公告)日：2002-12-05

申请号：US10174918

申请日：2002-06-19

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Eugene Owen ,  Raul Zegers Diaz ,  Osvaldo Colavin

IPC: G06F015/167 ,  G06F012/00

CPC classification number: G06T1/60 ,  G06F13/1605 ,  G06F13/18 ,  G06F15/167 ,  G09G5/001 ,  G09G5/363 ,  G09G2340/02 ,  G09G2360/18 ,  H04N19/423 ,  H04N19/427 ,  H04N19/61 ,  H04N21/443 ,  H04N21/4435

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

公开(公告)号：US20040088526A1

公开(公告)日：2004-05-06

申请号：US10283709

申请日：2002-10-30

Applicant: STMICROELECTRONICS, INC.

Inventor： Osvaldo Colavin ,  Davide Rizzo

IPC: G06F009/44

CPC classification number: G06F9/30043 ,  G06F9/30072

Abstract: Full predication of instruction execution is provided by operand predicates, where each operand has an associated predicate bit intuitively indicating the validity of the operand value. In a programmable processor supporting operand predication, an instruction will execute only if the predicate bit of every register containing a source operand is true. The predicate bit, if any, of the destination register is set to the logical AND of the source registers' predicates. Similarly, in a non-programmable processor synthesized with predicated operand support, an operator will perform the associated function depending on the state of inputs' predicates. The output predicate is evaluated as the logical AND of the inputs' predicates. An additional bit for each data register, a change in the semantics of the instructions to include predication, and a few additional instructions to save and restore register predicate bits and to specifically set or reset a register's predicate bit are required.

Abstract translation: 指令执行的完全预测由操作数谓词提供，其中每个操作数具有相关联的谓词比特，直观地指示操作数值的有效性。 在支持操作数预测的可编程处理器中，只有当包含源操作数的每个寄存器的谓词位都为真时，才执行指令。 目标寄存器的谓词位（如果有的话）被设置为源寄存器的谓词的逻辑AND。 类似地，在用预定操作数支持合成的非可编程处理器中，操作者将根据输入谓词的状态来执行相关联的功能。 输出谓词被评估为输入谓词的逻辑AND。 需要每个数据寄存器的附加位，指令包含预测的语义的变化以及保存和恢复寄存器谓词位以及特别设置或复位寄存器谓词位的附加指令。

公开(公告)号：US20040103263A1

公开(公告)日：2004-05-27

申请号：US10301372

申请日：2002-11-21

Applicant: STMICROELECTRONICS, INC.

Inventor： Osvaldo Colavin ,  Davide Rizzo

IPC: G06F015/00

CPC classification number: G06F9/3885 ,  G06F9/3012 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3853 ,  G06F9/3879 ,  G06F9/3891 ,  G06F15/8007 ,  G06F15/8015

Abstract: Clustered VLIW processing elements, each preferably simple and identical, are coupled by a runtime reconfigurable inter-cluster interconnect to form a coprocessor executing only those portions of a program having high instruction level parallelism. The initial portion of each program segment executed by the coprocessor reconfigures the interconnect, if necessary, or is skipped. Clusters may be directly connected to a subset of neighboring clusters, or indirectly connected to any other cluster, a hierarchy exposed to the programming model and enabling a larger number of clusters to be employed. The coprocessor is idled during remaining portions of the program to reduce power dissipation.

Abstract translation: 集群的VLIW处理元件，每个优选地是简单的和相同的，通过运行时可重配置的群间互连来耦合，以形成仅执行具有高指令级并行性的程序的那些部分的协处理器。 由协处理器执行的每个程序段的初始部分如果需要重新配置互连，或者被跳过。 集群可以直接连接到相邻集群的子集，或者间接地连接到任何其他集群，暴露于编程模型的层次结构，并且能够使用更多数量的集群。 协处理器在程序的剩余部分空闲，以减少功耗。

公开(公告)号：US20040088592A1

公开(公告)日：2004-05-06

申请号：US10284006

申请日：2002-10-30

Applicant: STMICROELECTRONICS, INC.

Inventor： Davide Rizzo ,  Osvaldo Colavin

IPC: G06F001/32

CPC classification number: G06F8/4432 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/41

Abstract: A coprocessor executing one among a set of candidate kernel loops within an application operates at the minimal clock frequency satisfying schedule constraints imposed by the compiler and data bandwidth constraints. The optimal clock frequency is statically determined by the compiler and enforced at runtime by software-controlled clock circuitry. Power dissipation savings and optimal resource usage are therefore achieved by the adaptation at runtime of the coprocessor clock rate for each of the various kernel loop implementations.

Abstract translation: 在应用程序中的一组候选内核循环中执行一个协处理器以满足由编译器施加的调度约束和数据带宽约束的最小时钟频率操作。 最佳时钟频率由编译器静态确定，并由运行时由软件控制的时钟电路执行。 因此，通过在运行时对各种内核循环实现中的每一个的协处理器时钟速率进行适应来实现功耗节省和最佳资源使用。