公开(公告)号：US11735460B2

公开(公告)日：2023-08-22

申请号：US17387861

申请日：2021-07-28

Applicant: QROMIS, Inc.

Inventor： Vladimir Odnoblyudov ,  Dilip Risbud ,  Ozgur Aktas ,  Cem Basceri

IPC: H01L29/778 ,  H01L21/683 ,  H01L21/762 ,  H01L29/861 ,  H01L21/285 ,  H01L21/18 ,  H01L21/02 ,  H01L21/28 ,  H01L21/48 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  C30B25/18 ,  C30B29/06 ,  C30B29/40 ,  H01L29/872 ,  H01L29/40

CPC classification number: H01L21/6835 ,  C30B25/183 ,  C30B29/06 ,  C30B29/406 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/02428 ,  H01L21/02458 ,  H01L21/18 ,  H01L21/28264 ,  H01L21/28587 ,  H01L21/4807 ,  H01L21/762 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66143 ,  H01L29/66204 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/861 ,  H01L29/8613 ,  H01L29/872 ,  H01L29/1066 ,  H01L29/402 ,  H01L2221/6835 ,  H01L2221/68345

Abstract: An integrated circuit device includes an engineered substrate including a substantially single crystal layer and a buffer layer coupled to the substantially single crystal layer. The integrated circuit device also includes a plurality of semiconductor devices coupled to the buffer layer. The plurality of semiconductor devices can include a first power device coupled to a first portion of the buffer layer and a second power device coupled to a second portion of the buffer layer. The first power device includes a first channel region comprising a first end, a second end, and a first central portion disposed between the first end and the second end. The second power device includes a second channel region comprising a third end, a fourth end, and a second central portion disposed between the third end and the fourth end.

公开(公告)号：US20230260784A1

公开(公告)日：2023-08-17

申请号：US18140926

申请日：2023-04-28

Applicant: ASM IP Holding B.V.

Inventor： Tom Blomberg ,  Chiyu Zhu

IPC: H01L21/02 ,  H01L21/28 ,  C23C16/40 ,  C23C16/455

CPC classification number: H01L21/02565 ,  H01L21/0262 ,  H01L21/0257 ,  H01L21/28194 ,  H01L21/0228 ,  C23C16/407 ,  C23C16/45527 ,  C23C16/401 ,  C23C16/45523 ,  H01L21/02592

Abstract: Methods for forming a doped metal oxide film on a substrate by cyclical deposition are provided. In some embodiments, methods may include contacting the substrate with a first reactant comprising a metal halide source, contacting the substrate with a second reactant comprising a hydrogenated source and contacting the substrate with a third reactant comprising an oxide source. In some embodiments, related semiconductor device structures may include a doped metal oxide film formed by cyclical deposition processes.

公开(公告)号：US20230231050A1

公开(公告)日：2023-07-20

申请号：US17661340

申请日：2022-04-29

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yutong SHEN ,  Jifeng TANG

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/08 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L29/7848 ,  H01L21/0257 ,  H01L21/02532 ,  H01L21/28518 ,  H01L29/45 ,  H01L29/161 ,  H01L29/0847

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes: a base, including a doped region; a recess, located in the doped region; and a gradient layer, filling the recess, wherein a doping concentration of the gradient layer varies gradually from a bottom of the recess upwards.

公开(公告)号：US20230223255A1

公开(公告)日：2023-07-13

申请号：US18153272

申请日：2023-01-11

Applicant: ASM IP Holding, B.V.

Inventor： Steven Van Aerde ,  Wilco Verweij ,  Bert Jongbloed ,  Dieter Pierreux ,  Kelly Houben ,  Rami Khazaka ,  Frederick Aryeetey ,  Peter Westrom ,  Omar Elleuch ,  Caleb Miskin

IPC: H01L21/02 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68

CPC classification number: H01L21/0257 ,  C30B25/165 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  H01L21/0262 ,  H01L21/02532

Abstract: A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing the plurality of substrates to a process chamber. A plurality of deposition cycles is executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial stack comprises a plurality of epitaxial pairs, wherein the epitaxial pairs each comprises a first epitaxial layer and a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. Each deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer. The first deposition pulse or the second deposition pulse further comprises a provision of a dopant precursor gas to the process chamber.

公开(公告)号：US11676813B2

公开(公告)日：2023-06-13

申请号：US17025009

申请日：2020-09-18

Applicant: Applied Materials, Inc.

Inventor： Aykut Aydin ,  Rui Cheng ,  Yi Yang ,  Krishna Nittala ,  Karthik Janakiraman ,  Bo Qi ,  Abhijit Basu Mallick

IPC: H01L21/02 ,  H01L21/324 ,  H01J37/32 ,  C23C16/56 ,  C23C16/50 ,  C23C16/30 ,  C23C16/24

CPC classification number: H01L21/0257 ,  C23C16/24 ,  C23C16/30 ,  C23C16/50 ,  C23C16/56 ,  H01J37/3244 ,  H01L21/02532 ,  H01L21/324 ,  H01J2237/332

Abstract: Exemplary deposition methods may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include delivering a dopant-containing precursor with the silicon-containing precursor and the boron-containing precursor. The dopant-containing precursor may include one or more of carbon, nitrogen, oxygen, or sulfur. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-and-boron material on a substrate disposed within the processing region of the semiconductor processing chamber. The silicon-and-boron material may include greater than or about 1 at. % of a dopant from the dopant-containing precursor.

公开(公告)号：US11646206B2

公开(公告)日：2023-05-09

申请号：US17101950

申请日：2020-11-23

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Brian Beatty ,  John Mark Meldrim ,  Yongjun Jeff Hu ,  Jordan D. Greenlee

IPC: H01L21/02 ,  C23C16/28 ,  C01G41/00

CPC classification number: H01L21/02645 ,  C01G41/00 ,  C23C16/28 ,  H01L21/0257 ,  C01P2006/40

Abstract: Described are methods for forming a multilayer conductive structure for semiconductor devices. A seed layer is formed comprising a metal and an additional constituent that in combination with the metal inhibits nucleation of a fill layer of the metal formed over the seed layer. Tungsten may be doped or alloyed with silicon to form the seed layer, with a tungsten fill being formed over the seed layer.

公开(公告)号：US20190214251A1

公开(公告)日：2019-07-11

申请号：US16305735

申请日：2017-05-31

Applicant: LASER SYSTEMS & SOLUTIONS OF EUROPE

Inventor： Fulvio MAZZAMUTO

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/268

CPC classification number: H01L21/02381 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02675 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/268

Abstract: Disclosed is a process for manufacturing a deep junction electronic device including steps of: b) Depositing a layer of non-monocrystalline semiconductor material on a plane surface of a substrate of a monocrystalline semiconductor material; c) Incorporating inactivated dopant elements prior to step b) into said substrate (1) and/or, respectively, during or after step b) into said layer, so as to form an inactivated doped layer; d) Exposing, an external surface of the layer formed at step b) to a laser thermal anneal beam, so as to melt said layer down to the substrate and so as to activate said dopant elements incorporated at step c); e) Stopping exposure to the laser beam so as to induce epi-like crystallization of the melted layer, so that said substrate and/or, respectively, an epi-like monocrystalline semiconductor material, comprises a layer of activated doped monocrystalline semiconductor material.

公开(公告)号：US20190165181A1

公开(公告)日：2019-05-30

申请号：US16054266

申请日：2018-08-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bahman Hekmatshoartabari ,  Ghavam Shahidi

IPC: H01L29/786 ,  H01L21/02

CPC classification number: H01L29/78621 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02686 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78675

Abstract: A method of forming a thin film transistor (TFT) that includes forming a low temperature polysilicon semiconductor layer on a substrate; and implanting first dopant regions on opposing sides of a channel region of the low temperature polysilicon semiconductor layer. The method may further include epitaxially forming second dopant regions on the first dopant regions. The concentration of the conductivity type dopant in the second dopant regions is greater than a concentration of the conductivity type dopant in the first dopant region. The second dopant regions are formed using a low temperature epitaxial deposition process at a temperature less than 350° C.

公开(公告)号：US20190131399A1

公开(公告)日：2019-05-02

申请号：US15797703

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao LIU ,  Huicheng CHANG ,  Chia-Cheng CHEN ,  Liang-Yin CHEN ,  Kuo-Ju CHEN ,  Chun-Hung WU ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L21/265 ,  H01L21/285 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US10020303B2

公开(公告)日：2018-07-10

申请号：US14666464

申请日：2015-03-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Renesas Electronics Corporation

Inventor： Hong He ,  Shogo Mochizuki ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3105 ,  H01L27/088 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/306 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/02271 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods for forming semiconductor devices having non-merged fin extensions. Methods for forming semiconductor devices include forming trenches in an insulator layer of a substrate. Fins are formed in the trenches and a dummy gate is formed over the fins, leaving a source and drain region exposed. The fins are etched below a surface level of a surrounding insulator layer. Fin extensions are epitaxially grown from the etched fins.