公开(公告)号：US20180286763A1

公开(公告)日：2018-10-04

申请号：US15942540

申请日：2018-04-01

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Loic GABEN

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/48 ,  H01L23/52 ,  H01L27/088

Abstract: A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other. Non-covered portions of the strip are doped to form source/drain regions. An insulating layer followed by a layer of a temporary material is then deposited. Certain ones of the sacrificial gates are left in place. Certain other ones of the sacrificial gates are replaced by a metal gate structure. The temporary material is then replaced with a conductive material to form contacts to the source/drain regions.

公开(公告)号：US20180330961A1

公开(公告)日：2018-11-15

申请号：US15979147

申请日：2018-05-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Loic GABEN

IPC: H01L21/306 ,  H01L21/02 ,  H01L21/311

Abstract: A planarization structure is formed with a planar upper face enclosing a relief projecting from a planar substrate. The process used deposits a layer of a first material over the reliefs and then forms a layer of a second material with a planar upper face. This second material may be etched selectively with respect to the first material. The second layer is processed so that the protuberances of the first material are uncovered. A planarizing is then performed on the first material as far as the layer of the second material by selective chemical-mechanical polishing with respect to the second material.

公开(公告)号：US20200020589A1

公开(公告)日：2020-01-16

申请号：US16582576

申请日：2019-09-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Loic GABEN

IPC: H01L21/8234 ,  H01L21/48 ,  H01L27/088 ,  H01L23/52 ,  H01L21/02

Abstract: A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other. Non-covered portions of the strip are doped to form source/drain regions. An insulating layer followed by a layer of a temporary material is then deposited. Certain ones of the sacrificial gates are left in place. Certain other ones of the sacrificial gates are replaced by a metal gate structure. The temporary material is then replaced with a conductive material to form contacts to the source/drain regions.

公开(公告)号：US20180330998A1

公开(公告)日：2018-11-15

申请号：US15973969

申请日：2018-05-08

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Loic GABEN

IPC: H01L21/84 ,  H01L21/225 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/2254 ,  H01L21/31111 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78696

Abstract: A strip or portions of a strip of silicon-germanium is made by first producing a strip of silicon suspended above a substrate. At least a portion of the strip of silicon is with a layer of silicon-germanium. Germanium enrichment of the portion of the strip of silicon is accomplished through a thermal oxidation. The resulting silicon oxide formed during the thermal oxidation is then removed.