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公开(公告)号：US20230329008A1
公开(公告)日：2023-10-12
申请号：US18335940
申请日：2023-06-15
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Remy BERTHELON , Olivier WEBER
IPC: H10B63/00
Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.
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公开(公告)号：US20220336736A1
公开(公告)日：2022-10-20
申请号：US17856711
申请日：2022-07-01
Inventor： Philippe BOIVIN , Daniel BENOIT , Remy BERTHELON
Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.
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公开(公告)号：US20180083006A1
公开(公告)日：2018-03-22
申请号：US15706952
申请日：2017-09-18
Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives , STMicroelectronics (CROLLES 2) SAS
Inventor： Francois ANDRIEU , Remy BERTHELON
IPC: H01L27/092 , H01L27/12 , H01L29/423 , H01L29/78
CPC classification number: H01L27/0922 , H01L21/823807 , H01L27/0207 , H01L27/092 , H01L27/1203 , H01L29/1054 , H01L29/4238 , H01L29/7848
Abstract: An integrated circuit is provided, including: a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and the second nMOS transistors including a channel region made of silicon that is subjected to tensile stress, and their respective gates being positioned at least 250 nm from a border of their active zone; and a third pair including a third nMOS transistor having a same construction as the second nMOS transistor and a third pMOS transistor having a same construction as the first pMOS transistor and having a tensile stress that is lower by at least 250 MPa than the tensile stress of the channel region, respective gates of the transistors of the third pair being positioned at most 200 nm from a border of their active zone.
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公开(公告)号：US20180083005A1
公开(公告)日：2018-03-22
申请号：US15706935
申请日：2017-09-18
Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives , STMICROELECTRONICS (CROLLES 2) SAS
Inventor： Francois ANDRIEU , Remy BERTHELON
IPC: H01L27/092 , H01L29/78 , H01L29/161 , H01L29/167
CPC classification number: H01L27/0922 , H01L21/823807 , H01L27/0207 , H01L27/092 , H01L29/1054 , H01L29/161 , H01L29/167 , H01L29/7842
Abstract: An integrated circuit is provided, including a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and second pMOS transistors including a channel that is subjected to compressive stress and made of an SiGe alloy, and a gate of said transistors being positioned at least 250 nm from a border of an active zone of said transistors; a third pair including a third nMOS transistor having a same construction as the first nMOS transistor and a third pMOS transistor having a same construction as the second pMOS transistor and exhibiting a compressive stress that is lower by at least 250 MPa, the gate of said transistors of the third pair being positioned at most 200 nm from the border.
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公开(公告)号：US20240147737A1
公开(公告)日：2024-05-02
申请号：US18491349
申请日：2023-10-20
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Olivier WEBER , Remy BERTHELON
Abstract: A method of manufacturing an electronic chip includes the following successive steps: a) forming of a first layer on top of and in contact with a second semiconductor layer, the second layer being on top of and in contact with a third semiconductor layer; b) doping of the first layer to form, on the second layer, a first doped sub-layer of the first conductivity type and a second doped sub-layer of the second conductivity type; c) forming of islands in the first layer organized in an array of rows and of columns at the surface of the second layer; and d) forming of memory cells based on a phase-change material on the islands of the first layer.
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Patent Agency Ranking
公开(公告)号：US20230309423A1
公开(公告)日：2023-09-28
申请号：US18321347
申请日：2023-05-22
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Remy BERTHELON , Franck ARNAUD
CPC classification number: H10N70/231 , H10B63/00 , H10N70/021 , H10N70/063 , H10N70/8828
Abstract: An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.
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公开(公告)号：US20180331221A1
公开(公告)日：2018-11-15
申请号：US15976452
申请日：2018-05-10
Applicant: STMicroelectronics (Crolles 2) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
Inventor： Remy BERTHELON , Francois ANDRIEU
IPC: H01L29/78 , H01L27/092 , H01L27/12 , H01L21/84 , H01L21/8238
CPC classification number: H01L29/7847 , H01L21/76283 , H01L21/823807 , H01L21/84 , H01L27/0207 , H01L27/092 , H01L27/1203 , H01L29/7849
Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strips. Transverse trenches extend from one edge to another edge of the first strip to define tensilely strained semiconductor slabs in the first strip, with the second strip including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip, P-channel MOS transistors are located inside and on top of the portions.
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公开(公告)号：US20230411450A1
公开(公告)日：2023-12-21
申请号：US18330287
申请日：2023-06-06
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Remy BERTHELON , Olivier WEBER
IPC: H01L29/06 , H01L21/762 , H01L21/321
CPC classification number: H01L29/0649 , H01L21/76229 , H01L21/3212 , H10B63/10
Abstract: The present description concerns a method of manufacturing a device comprising a first portion having an array of memory cells formed therein and a second portion having transistors formed therein, the method comprising: a. the forming of first insulating trenches separating from one another the substrate regions of a same cell row, and b. the forming of second trenches separating from one another the regions of a same cell column, the second trenches having a height greater than the height of the first trenches, step a. comprising the independent forming of a lower portion and of an upper portion of each first trench, the forming of the upper portions comprising the deposition of a first insulating layer, the etching of the portions of the first insulating layer which are not located on the upper portions.
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公开(公告)号：US20210343788A1
公开(公告)日：2021-11-04
申请号：US17244514
申请日：2021-04-29
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Remy BERTHELON , Olivier WEBER
IPC: H01L27/24
Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.
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公开(公告)号：US20210305502A1
公开(公告)日：2021-09-30
申请号：US17216193
申请日：2021-03-29
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Remy BERTHELON , Franck ARNAUD
Abstract: An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.
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