公开(公告)号：US10741565B2

公开(公告)日：2020-08-11

申请号：US16379476

申请日：2019-04-09

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics (Crolles 2) SAS

Inventor： Francois Andrieu ,  Remy Berthelon ,  Bastien Giraud

IPC: G11C11/41 ,  H01L27/11 ,  G11C11/419 ,  H01L21/822 ,  H01L27/06 ,  H01L27/12

Abstract: The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.

公开(公告)号：US12144187B2

公开(公告)日：2024-11-12

申请号：US18335940

申请日：2023-06-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Remy Berthelon ,  Olivier Weber

IPC: H10B63/00

Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.

公开(公告)号：US10418486B2

公开(公告)日：2019-09-17

申请号：US15976452

申请日：2018-05-10

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Remy Berthelon ,  Francois Andrieu

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/02 ,  H01L27/12 ,  H01L27/092 ,  H01L21/762 ,  H01L29/786

Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strips. Transverse trenches extend from one edge to another edge of the first strip to define tensilely strained semiconductor slabs in the first strip, with the second strip including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip, P-channel MOS transistors are located inside and on top of the portions.

公开(公告)号：US10446548B2

公开(公告)日：2019-10-15

申请号：US15706952

申请日：2017-09-18

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Francois Andrieu ,  Remy Berthelon

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/10 ,  H01L27/02

Abstract: An integrated circuit is provided, including: a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and the second nMOS transistors including a channel region made of silicon that is subjected to tensile stress, and their respective gates being positioned at least 250 nm from a border of their active zone; and a third pair including a third nMOS transistor having a same construction as the second nMOS transistor and a third pMOS transistor having a same construction as the first pMOS transistor and having a tensile stress that is lower by at least 250 MPa than the tensile stress of the channel region, respective gates of the transistors of the third pair being positioned at most 200 nm from a border of their active zone.

公开(公告)号：US10263110B2

公开(公告)日：2019-04-16

申请号：US15387712

申请日：2016-12-22

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Remy Berthelon ,  Didier Dutartre ,  Pierre Morin ,  Francois Andrieu ,  Elise Baylac

IPC: H01L29/207 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

Abstract: A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.

公开(公告)号：US11723220B2

公开(公告)日：2023-08-08

申请号：US17244514

申请日：2021-04-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Remy Berthelon ,  Olivier Weber

IPC: H10B63/00

CPC classification number: H10B63/32 ,  H10B63/80

Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.

公开(公告)号：US11690303B2

公开(公告)日：2023-06-27

申请号：US17216193

申请日：2021-03-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Remy Berthelon ,  Franck Arnaud

IPC: G11C11/00 ,  H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10B63/00 ,  H10N70/021 ,  H10N70/063 ,  H10N70/8828

Abstract: An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.

公开(公告)号：US20190312039A1

公开(公告)日：2019-10-10

申请号：US16379476

申请日：2019-04-09

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics (Crolles 2) SAS

Inventor： Francois Andrieu ,  Remy Berthelon ,  Bastien Giraud

IPC: H01L27/11 ,  G11C11/419

Abstract: The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.

公开(公告)号：US12167703B2

公开(公告)日：2024-12-10

申请号：US18321347

申请日：2023-05-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Remy Berthelon ,  Franck Arnaud

IPC: G11C11/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

Abstract: An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.

公开(公告)号：US11800821B2

公开(公告)日：2023-10-24

申请号：US17856711

申请日：2022-07-01

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin ,  Daniel Benoit ,  Remy Berthelon

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10B63/30 ,  H10N70/021 ,  H10N70/826

Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.