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公开(公告)号：US20210109708A1
公开(公告)日：2021-04-15
申请号：US17039108
申请日：2020-09-30
Inventor： Rene Peyrard , Fabrice Romain
IPC: G06F7/40
Abstract: An embodiment method for determining a carry digit indicator bit of a first binary datum includes a step for processing of the first binary datum masked by a masking operation, and not including any processing step of the first binary datum.
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公开(公告)号：US12149250B2
公开(公告)日：2024-11-19
申请号：US17412991
申请日：2021-08-26
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Denis Cottin , Fabrice Romain
IPC: H03K3/356 , G09G3/3225 , H03K19/0185
Abstract: An output potential level among two first levels is delivered according to an input level among two second levels. The output potential level is delivered at a first node connecting together first and second transistors electrically in series between two second nodes of application of the first levels. A first DC voltage defining a high limit for the control voltage of the first transistor is delivered by a first voltage generator powered by one of the second nodes. A second DC voltage defining a high limit for the control voltage of the second transistor is delivered by a second voltage generator controlled by a value representative of the first voltage and powered between the second nodes.
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公开(公告)号：US11762633B2
公开(公告)日：2023-09-19
申请号：US17039353
申请日：2020-09-30
Inventor： Rene Peyrard , Fabrice Romain
CPC classification number: G06F7/764 , G06F7/4824 , G06F7/49942
Abstract: The present disclosure relates to a circuit and method for determining a sign indicator bit of a binary datum including a step for processing of the binary datum masked with a masking operation, and not including any processing step of the binary datum.
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Patent Agency Ranking
公开(公告)号：US20210109713A1
公开(公告)日：2021-04-15
申请号：US17038584
申请日：2020-09-30
Inventor： Rene Peyrard , Fabrice Romain
Abstract: The present disclosure relates to a device and method for processing masked binary data values, comprising extracting and inserting a first part of a first masked binary data value in a second masked binary data value, in which the first and second masked binary data values stay masked throughout all of the processing.
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公开(公告)号：US11922133B2
公开(公告)日：2024-03-05
申请号：US17038774
申请日：2020-09-30
Inventor： Rene Peyrard , Fabrice Romain , Jean-Michel Derien , Christophe Eichwald
Abstract: A method includes processing, by an arithmetic and logic unit of a processor, masked data, and keeping, by the arithmetic and logic unit of the processor, the masked data masked throughout their processing by the arithmetic and logic unit. A processor includes an arithmetic and logic unit configured to keep masked data masked throughout processing of the masked data in the arithmetic and logic unit.
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公开(公告)号：US11714604B2
公开(公告)日：2023-08-01
申请号：US17039108
申请日：2020-09-30
Inventor： Rene Peyrard , Fabrice Romain
IPC: G06F7/40
CPC classification number: G06F7/405
Abstract: An embodiment method for determining a carry digit indicator bit of a first binary datum includes a step for processing of the first binary datum masked by a masking operation, and not including any processing step of the first binary datum.
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公开(公告)号：US20210109714A1
公开(公告)日：2021-04-15
申请号：US17039353
申请日：2020-09-30
Inventor： Rene Peyrard , Fabrice Romain
Abstract: The present disclosure relates to a circuit and method for determining a sign indicator bit of a binary datum including a step for processing of the binary datum masked with a masking operation, and not including any processing step of the binary datum.
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公开(公告)号：US20210109711A1
公开(公告)日：2021-04-15
申请号：US17038774
申请日：2020-09-30
Inventor： Rene Peyrard , Fabrice Romain , Jean-Michel Derien , Christophe Eichwald
Abstract: An embodiment relates to a method for processing masked data using a processor comprising an arithmetic and logic unit, in which the masked data remain masked during their processing in the arithmetic and logic unit.
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