公开(公告)号：US09448951B2

公开(公告)日：2016-09-20

申请号：US13705435

申请日：2012-12-05

Applicant: STMicroelectronics (R&D) Ltd.

Inventor： David Smith

IPC: G06F13/12 ,  G06F13/10 ,  G06F3/06 ,  G06F13/16 ,  G06F15/167 ,  G06F1/10 ,  G06F5/06 ,  G06F13/42

CPC classification number: G06F13/102 ,  G06F1/10 ,  G06F3/061 ,  G06F3/0614 ,  G06F5/06 ,  G06F13/16 ,  G06F13/423 ,  G06F15/167

Abstract: A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral configured to communicate with at least one further processor memory mapped peripheral to control the sharing of the data, wherein the memory mapped peripheral includes a sender part including a data request generator configured to output a data request indicator to the further processor module dependent on a data request register write signal from the processor; and an acknowledgement waiting signal generator configured to output an acknowledgement waiting signal to the processor dependent on a data acknowledgement signal from the further processor module, wherein the data request generator data request indicator is further dependent on the data acknowledgement signal and the acknowledgement waiting signal generator acknowledgement waiting signal is further dependent on the acknowledgement waiting register write signal.

Abstract translation: 一种处理器模块，包括配置成与至少一个另外的处理器模块处理器共享数据的处理器; 以及存储器映射外设，被配置为与至少一个另外的处理器存储器映射的外围设备通信以控制所述数据的共享，其中所述存储器映射的外围设备包括发送器部分，所述发送器部分包括数据请求生成器， 取决于来自处理器的数据请求寄存器写入信号的模块; 以及确认等待信号发生器，其被配置为根据来自所述另外的处理器模块的数据确认信号将确认等待信号输出到所述处理器，其中所述数据请求生成器数据请求指示符还依赖于所述数据确认信号和所述确认等待信号发生器 确认等待信号还取决于确认等待寄存器写入信号。

公开(公告)号：US20130151792A1

公开(公告)日：2013-06-13

申请号：US13705435

申请日：2012-12-05

Applicant: STMicroelectronics (R&D) Ltd.

Inventor： David Smith

IPC: G06F3/06

CPC classification number: G06F13/102 ,  G06F1/10 ,  G06F3/061 ,  G06F3/0614 ,  G06F5/06 ,  G06F13/16 ,  G06F13/423 ,  G06F15/167

Abstract: A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral configured to communicate with at least one further processor memory mapped peripheral to control the sharing of the data, wherein the memory mapped peripheral includes a sender part including a data request generator configured to output a data request indicator to the further processor module dependent on a data request register write signal from the processor; and an acknowledgement waiting signal generator configured to output an acknowledgement waiting signal to the processor dependent on a data acknowledgement signal from the further processor module, wherein the data request generator data request indicator is further dependent on the data acknowledgement signal and the acknowledgement waiting signal generator acknowledgement waiting signal is further dependent on the acknowledgement waiting register write signal.

Abstract translation: 一种处理器模块，包括配置成与至少一个另外的处理器模块处理器共享数据的处理器; 以及存储器映射外设，被配置为与至少一个另外的处理器存储器映射的外围设备通信以控制所述数据的共享，其中所述存储器映射的外围设备包括发送器部分，所述发送器部分包括数据请求生成器， 取决于来自处理器的数据请求寄存器写入信号的模块; 以及确认等待信号发生器，其被配置为根据来自所述另外的处理器模块的数据确认信号将确认等待信号输出到所述处理器，其中所述数据请求生成器数据请求指示符还依赖于所述数据确认信号和所述确认等待信号发生器 确认等待信号还取决于确认等待寄存器写入信号。