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公开(公告)号：US09448951B2
公开(公告)日：2016-09-20
申请号：US13705435
申请日：2012-12-05
Applicant: STMicroelectronics (R&D) Ltd.
Inventor： David Smith
CPC classification number: G06F13/102 , G06F1/10 , G06F3/061 , G06F3/0614 , G06F5/06 , G06F13/16 , G06F13/423 , G06F15/167
Abstract: A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral configured to communicate with at least one further processor memory mapped peripheral to control the sharing of the data, wherein the memory mapped peripheral includes a sender part including a data request generator configured to output a data request indicator to the further processor module dependent on a data request register write signal from the processor; and an acknowledgement waiting signal generator configured to output an acknowledgement waiting signal to the processor dependent on a data acknowledgement signal from the further processor module, wherein the data request generator data request indicator is further dependent on the data acknowledgement signal and the acknowledgement waiting signal generator acknowledgement waiting signal is further dependent on the acknowledgement waiting register write signal.
Abstract translation: 一种处理器模块，包括配置成与至少一个另外的处理器模块处理器共享数据的处理器; 以及存储器映射外设，被配置为与至少一个另外的处理器存储器映射的外围设备通信以控制所述数据的共享，其中所述存储器映射的外围设备包括发送器部分，所述发送器部分包括数据请求生成器， 取决于来自处理器的数据请求寄存器写入信号的模块; 以及确认等待信号发生器，其被配置为根据来自所述另外的处理器模块的数据确认信号将确认等待信号输出到所述处理器，其中所述数据请求生成器数据请求指示符还依赖于所述数据确认信号和所述确认等待信号发生器 确认等待信号还取决于确认等待寄存器写入信号。
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公开(公告)号：US09313427B2
公开(公告)日：2016-04-12
申请号：US13710981
申请日：2012-12-11
Applicant: STMicroelectronics (R&D) Ltd
Inventor： John Kevin Moore , Matthew Purcell , Graeme Storm , Tarek Lule
IPC: H04N5/369 , H04N5/353 , H01L27/146 , H04N5/335 , H01L27/148 , H04N5/3745 , H04N9/04 , H04N5/374
CPC classification number: H04N5/3535 , H01L27/146 , H01L27/14603 , H01L27/14621 , H01L27/148 , H04N5/335 , H04N5/369 , H04N5/3745 , H04N9/045
Abstract: An image sensor having improved dynamic range includes a signal that is read out for a selection of pixels which act as a calibration to govern the choice of exposure levels to be applied to the rest of the array. In this way, the sensor is operable to adapt to variations in scene intensity. The pixels in the array are vertically and horizontally addressed so as to enable accounted for small areas of intensity variation across an imaged scene.
Abstract translation: 具有改进的动态范围的图像传感器包括读出用于选择像素的信号，该像素用作校准以控制要应用于阵列的其余部分的曝光电平的选择。 以这种方式，传感器可操作以适应场景强度的变化。 阵列中的像素被垂直和水平地寻址，使得能够占据成像场景的强度变化的小区域。
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公开(公告)号：US20130155282A1
公开(公告)日：2013-06-20
申请号：US13710198
申请日：2012-12-10
Applicant: STMicroelectronics (R&D) Ltd.
Inventor： Robert Golding
IPC: H01L27/146 , H04N5/335
CPC classification number: H01L27/14609 , G01N21/645 , H04N5/335 , H04N5/35572 , H04N5/378
Abstract: A pixel readout circuit including at least first, second and third memory locations. During an integration period of a pixel, the pixel readout circuit repeatedly samples the pixel output level during the integration period, stores the first sample in the first memory location, and stores each subsequent sample in memory locations other than the first memory location. Each sample is stored with a time corresponding to when that sample was taken, such that at any one time subsequent to the first three samples having been stored, at least the first sample and the two most recent samples are stored. Also disclosed is a corresponding method of reading out of a pixel output over an undefined integration period.
Abstract translation: 一种像素读出电路，至少包括第一，第二和第三存储单元。 在像素的积分期间，像素读出电路在积分期间反复取样像素输出电平，将第一样本存储在第一存储器位置，并将每个后续样本存储在第一存储单元以外的存储位置。 存储每个样品的时间对应于该采样时间，使得在存储了前三个样品之后的任何一个时间，至少存储了第一样品和两个最近的样品。 还公开了一种在未定义的积分周期内读出像素输出的相应方法。
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公开(公告)号：US20130151792A1
公开(公告)日：2013-06-13
申请号：US13705435
申请日：2012-12-05
Applicant: STMicroelectronics (R&D) Ltd.
Inventor： David Smith
IPC: G06F3/06
CPC classification number: G06F13/102 , G06F1/10 , G06F3/061 , G06F3/0614 , G06F5/06 , G06F13/16 , G06F13/423 , G06F15/167
Abstract: A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral configured to communicate with at least one further processor memory mapped peripheral to control the sharing of the data, wherein the memory mapped peripheral includes a sender part including a data request generator configured to output a data request indicator to the further processor module dependent on a data request register write signal from the processor; and an acknowledgement waiting signal generator configured to output an acknowledgement waiting signal to the processor dependent on a data acknowledgement signal from the further processor module, wherein the data request generator data request indicator is further dependent on the data acknowledgement signal and the acknowledgement waiting signal generator acknowledgement waiting signal is further dependent on the acknowledgement waiting register write signal.
Abstract translation: 一种处理器模块，包括配置成与至少一个另外的处理器模块处理器共享数据的处理器; 以及存储器映射外设，被配置为与至少一个另外的处理器存储器映射的外围设备通信以控制所述数据的共享，其中所述存储器映射的外围设备包括发送器部分，所述发送器部分包括数据请求生成器， 取决于来自处理器的数据请求寄存器写入信号的模块; 以及确认等待信号发生器，其被配置为根据来自所述另外的处理器模块的数据确认信号将确认等待信号输出到所述处理器，其中所述数据请求生成器数据请求指示符还依赖于所述数据确认信号和所述确认等待信号发生器 确认等待信号还取决于确认等待寄存器写入信号。
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公开(公告)号：US09164903B2
公开(公告)日：2015-10-20
申请号：US13650503
申请日：2012-10-12
Applicant: STMicroelectronics (R&D) Ltd.
Inventor： Davide Sarta
IPC: G06F12/06
CPC classification number: G06F12/0646 , G06F12/06 , G06F12/0607
Abstract: A memory management device including a plurality of outputs, each output configured to interface to respective one of a plurality of memories; and a controller configured to cause each buffer allocated to the memories to be divided up substantially equally between each of the plurality of memories.
Abstract translation: 一种包括多个输出的存储器管理装置，每个输出被配置为与多个存储器中的相应一个存储器接口; 以及控制器，其被配置为使得分配给所述存储器的每个缓冲器在所述多个存储器中的每一个之间基本上相等地被划分。
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Patent Agency Ranking
公开(公告)号：US20130222623A1
公开(公告)日：2013-08-29
申请号：US13856865
申请日：2013-04-04
Applicant: STMICROELECTRONICS (R&D) LTD.
Inventor： STUART MCLEOD
IPC: H04N5/232
CPC classification number: H04N5/23251 , H04N5/23248 , H04N5/23254 , H04N5/23258 , H04N5/23287
Abstract: A method of motion compensation in a camera may include deriving a motion signal representative of a motion of the camera, processing video frames of a video signal from an image sensor of the camera during a viewfinder mode to derive motion vectors between pairs of frames, and processing the motion signal with a number of combinations of gain and offset factors during the viewfinder mode. The method may also include determining combinations for producing threshold motion vectors, and applying the combination producing the threshold motion vectors for processing the motion signal during a still capture mode to produce a control signal for a motion compensating element for optics of the camera.
Abstract translation: 在相机中的运动补偿的方法可以包括导出表示相机的运动的运动信号，在取景器模式期间处理来自相机的图像传感器的视频信号的视频帧，以导出帧对之间的运动矢量，以及 在取景器模式期间用增益和偏移因子的多种组合处理运动信号。 该方法还可以包括确定用于产生阈值运动矢量的组合，以及应用产生用于在静止捕捉模式期间处理运动信号的阈值运动矢量的组合以产生用于相机光学装置的运动补偿元件的控制信号。
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公开(公告)号：US20130155239A1
公开(公告)日：2013-06-20
申请号：US13710981
申请日：2012-12-11
Inventor： John Kevin Moore , Matthew Purcell , Graeme Storm , Tarek Lule
IPC: H04N5/335
CPC classification number: H04N5/3535 , H01L27/146 , H01L27/14603 , H01L27/14621 , H01L27/148 , H04N5/335 , H04N5/369 , H04N5/3745 , H04N9/045
Abstract: An image sensor having improved dynamic range includes a signal that is read out for a selection of pixels which act as a calibration to govern the choice of exposure levels to be applied to the rest of the array. In this way, the sensor is operable to adapt to variations in scene intensity. The pixels in the array are vertically and horizontally addressed so as to enable accounted for small areas of intensity variation across an imaged scene.
Abstract translation: 具有改进的动态范围的图像传感器包括读出用于选择像素的信号，该像素用作校准以控制要应用于阵列的其余部分的曝光电平的选择。 以这种方式，传感器可操作以适应场景强度的变化。 阵列中的像素被垂直和水平地寻址，使得能够占据成像场景的强度变化的小区域。
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公开(公告)号：US08873668B2
公开(公告)日：2014-10-28
申请号：US13651883
申请日：2012-10-15
Applicant: STMicroelectronics SA , STMicroelectronics (R&D) Ltd , STMicroelectronics (Grenoble 2) SAS
Inventor： Andrew Ferris , Ignazio Antonino Urzi , Pascal Teissier
IPC: H04L25/34
CPC classification number: G06F13/423
Abstract: A circuit includes a first n-bit communications block and a second m-bit communications block. A controller is configured to control mode of operation for the first and second communications blocks. In a first mode, the first and second communications blocks function as a single communications block for n+m bit communications. In a second mode, the first and second communications blocks operate as substantially independent communications block for n bit communications and m bit communications.
Abstract translation: 电路包括第一n比特通信块和第二m比特通信块。 控制器被配置为控制第一和第二通信块的操作模式。 在第一模式中，第一和第二通信块用作n + m位通信的单个通信块。 在第二模式中，第一和第二通信块作为用于n位通信和m位通信的基本上独立的通信块来操作。
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公开(公告)号：US20130306843A1
公开(公告)日：2013-11-21
申请号：US13937311
申请日：2013-07-09
Applicant: STMICROELECTRONICS (R&D) LTD.
Inventor： JUSTIN RICHARDSON
IPC: H04N5/378
CPC classification number: H04N5/378 , H01L27/14601 , H04N5/335 , H04N5/367
Abstract: An image sensor IC may have a non-volatile memory for several functions. The functions may include storing control parameters for a camera autofocus module, part tracking data, and data for defect correction or color science. The non-volatile memory can in particular be an antifuse non-volatile memory, which may not need special light shielding.
Abstract translation: 图像传感器IC可以具有用于若干功能的非易失性存储器。 功能可以包括存储用于相机自动对焦模块的控制参数，零件跟踪数据以及用于缺陷校正或色彩科学的数据。 非易失性存储器特别可以是反熔丝非易失性存储器，其可能不需要特殊的光屏蔽。
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公开(公告)号：US20130259115A1
公开(公告)日：2013-10-03
申请号：US13845299
申请日：2013-03-18
Applicant: STMICROELECTRONICS R&D LTD
Inventor： Peter Stieglitz
IPC: H04N7/26
CPC classification number: H04N19/436 , H04N19/44
Abstract: An audio/video processing device includes a first pipeline and a second pipeline. The first pipeline is configured to receive a first program stream and decode the first program stream. The second pipeline is configured to receive a second program stream and at least partially decode the second program stream. In response to selection of the first program stream, the first pipeline is further configured to output the decoded first program stream and the second pipeline is further configured to discard the partially decoded second program stream. In response to selection of the second program stream, the second pipeline is configured to fully decode the second program stream and output the decoded second program stream.
Abstract translation: 音频/视频处理设备包括第一管道和第二管道。 第一流水线被配置为接收第一程序流并对第一程序流进行解码。 第二流水线被配置为接收第二程序流并且至少部分地解码第二程序流。 响应于第一节目流的选择，第一流水线进一步被配置为输出解码的第一节目流，并且第二流水线进一步被配置为丢弃部分解码的第二节目流。 响应于第二节目流的选择，第二流水线被配置为完全解码第二节目流并输出解码的第二节目流。
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