公开(公告)号：US11593289B2

公开(公告)日：2023-02-28

申请号：US16516988

申请日：2019-07-19

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： François Cloute ,  Sandrine Lendre

IPC: G06F13/28

Abstract: A memory contains a linked list of records representative of a plurality of data transfers via a direct memory access control circuit. Each record is representative of parameters of an associated data transfer of the plurality of data transfers. The parameters of each record include a transfer start condition of the associated data transfer and a transfer end event of the associated data transfer.

公开(公告)号：US20180189205A1

公开(公告)日：2018-07-05

申请号：US15701003

申请日：2017-09-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Dragos Davidescu ,  Sandrine Lendre ,  Olivier Ferrand

IPC: G06F13/16 ,  G06F1/32 ,  G06F13/24

CPC classification number: G06F13/1673 ,  G06F1/3243 ,  G06F1/3293 ,  G06F13/24 ,  Y02D10/122 ,  Y02D10/152

Abstract: An embodiment system includes a first processor configured to process a suite of instructions and a second processor configured to process a subset of the suite of instructions. The system further includes a power management circuit configured to select the first processor or the second processor as a selected processor, the power management circuit being further configured to activate the selected processor or place the selected processor on standby. The system also includes a first peripheral device configured to generate a first interrupt signal, a switch configured to direct the first interrupt signal to the selected processor, and a first memory configured to store a first interrupt routine associated with the first interrupt signal, the selected processor being configured to execute the first interrupt routine in response to the first interrupt signal.

公开(公告)号：US20200026672A1

公开(公告)日：2020-01-23

申请号：US16516988

申请日：2019-07-19

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： François Cloute ,  Sandrine Lendre

IPC: G06F13/28

Abstract: A memory contains a linked list of records representative of a plurality of data transfers via a direct memory access control circuit. Each record is representative of parameters of an associated data transfer of the plurality of data transfers. The parameters of each record include a transfer start condition of the associated data transfer and a transfer end event of the associated data transfer.

公开(公告)号：US10402353B2

公开(公告)日：2019-09-03

申请号：US15701003

申请日：2017-09-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Dragos Davidescu ,  Sandrine Lendre ,  Olivier Ferrand

IPC: G06F13/16 ,  G06F1/3234 ,  G06F1/3293 ,  G06F13/24

Abstract: An embodiment system includes a first processor configured to process a suite of instructions and a second processor configured to process a subset of the suite of instructions. The system further includes a power management circuit configured to select the first processor or the second processor as a selected processor, the power management circuit being further configured to activate the selected processor or place the selected processor on standby. The system also includes a first peripheral device configured to generate a first interrupt signal, a switch configured to direct the first interrupt signal to the selected processor, and a first memory configured to store a first interrupt routine associated with the first interrupt signal, the selected processor being configured to execute the first interrupt routine in response to the first interrupt signal.