公开(公告)号：US09696351B2

公开(公告)日：2017-07-04

申请号：US14585357

申请日：2014-12-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Daljeet Kumar ,  Tapas Nandy ,  Surendra Kumar

IPC: G01R19/04 ,  G01R19/25

CPC classification number: G01R19/04 ,  G01R19/2503

Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

公开(公告)号：US10024888B2

公开(公告)日：2018-07-17

申请号：US15618269

申请日：2017-06-09

Applicant: STMicroelectronics International N.V.

Inventor： Daljeet Kumar ,  Tapas Nandy ,  Surendra Kumar

IPC: G01R19/04 ,  G01R19/25

Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

公开(公告)号：US20170276710A1

公开(公告)日：2017-09-28

申请号：US15618269

申请日：2017-06-09

Applicant: STMicroelectronics International N.V.

Inventor： Daljeet Kumar ,  Tapas Nandy ,  Surendra Kumar

IPC: G01R19/04 ,  G01R19/25

CPC classification number: G01R19/04 ,  G01R19/2503

Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

公开(公告)号：US20140111248A1

公开(公告)日：2014-04-24

申请号：US13656079

申请日：2012-10-19

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Daljeet Kumar

IPC: H03K5/24

CPC classification number: H03K5/24 ,  H04B3/46

Abstract: An analog disconnection envelope detection circuit having a low power supply detects a high speed, high differential voltage disconnect state on a data line. Level-shifting circuitry shifts the voltage level of two input signals by the value of a detection threshold voltage, generates differential signals used to indicate conditions of the input signals, and mitigates effects of input differential signal common-mode voltage on the detection operation. Circuitry is provided to equalize VDS of detecting tail current sources, thereby eliminating errors resulting from VDS mismatch of tail current sources. Comparator circuitry compares the sets of differential signals and indicates when the absolute difference between the two input signals is greater than a reference voltage. Output circuitry generates a disconnect signal corresponding to the disconnect condition. When compared to conventional disconnect detection circuitry, the disclosed circuit utilizes a relatively low supply voltage to detect high differential voltage disconnect conditions with improved accuracy.

Abstract translation: 具有低电源的模拟断路包络检测电路检测数据线上的高速，高差分电压断开状态。 电平移位电路通过检测阈值电压的值将两个输入信号的电压电平移位，产生用于指示输入信号条件的差分信号，并减轻输入差分信号共模电压对检测操作的影响。 提供电路以均衡检测尾电流源的VDS，从而消除由尾电流源的VDS失配引起的误差。 比较器电路比较差分信号的集合，并指示两个输入信号之间的绝对差大于参考电压的时间。 输出电路产生对应于断开条件的断开信号。 当与常规断开检测电路相比时，所公开的电路利用相对较低的电源电压来以更高的精度来检测高差分电压断开条件。

公开(公告)号：US09106219B2

公开(公告)日：2015-08-11

申请号：US14075272

申请日：2013-11-08

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Mayank Kumar Singh ,  Daljeet Kumar ,  Hiten Advani

IPC: H04L25/02 ,  G11C7/12 ,  H03K19/003

CPC classification number: H03K19/00346 ,  H04L25/0278 ,  H04L25/0298

Abstract: An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.

Abstract translation: 实施例包括具有校准器的阻抗校准电路，该校准器被配置为比较外部节点处的电压电平和阻抗校准电路的内部节点，并且基于该比较来生成输出。 校准器还包括耦合在外部节点和比较器的第一输入端之间以及内部节点和比较器的第二输入端之间的相应滤波器。 滤波器被配置为从内部节点处的可编程电阻器耦合到的芯片地线将对称噪声注入到比较器中。

公开(公告)号：US08829943B2

公开(公告)日：2014-09-09

申请号：US13656079

申请日：2012-10-19

Applicant: STMicroelectronics International N.V.

Inventor： Daljeet Kumar

IPC: H03K5/153

CPC classification number: H03K5/24 ,  H04B3/46

Abstract: An analog disconnection envelope detection circuit having a low power supply detects a high speed, high differential voltage disconnect state on a data line. Level-shifting circuitry shifts the voltage level of two input signals by the value of a detection threshold voltage, generates differential signals used to indicate conditions of the input signals, and mitigates effects of input differential signal common-mode voltage on the detection operation. Circuitry is provided to equalize VDS of detecting tail current sources, thereby eliminating errors resulting from VDS mismatch of tail current sources. Comparator circuitry compares the sets of differential signals and indicates when the absolute difference between the two input signals is greater than a reference voltage. Output circuitry generates a disconnect signal corresponding to the disconnect condition. When compared to conventional disconnect detection circuitry, the disclosed circuit utilizes a relatively low supply voltage to detect high differential voltage disconnect conditions with improved accuracy.

Abstract translation: 具有低电源的模拟断路包络检测电路检测数据线上的高速，高差分电压断开状态。 电平移位电路通过检测阈值电压的值移位两个输入信号的电压电平，产生用于指示输入信号条件的差分信号，并减轻输入差分信号共模电压对检测操作的影响。 提供电路以均衡检测尾电流源的VDS，从而消除由尾电流源的VDS失配引起的误差。 比较器电路比较差分信号的集合，并指示两个输入信号之间的绝对差大于参考电压的时间。 输出电路产生对应于断开条件的断开信号。 当与常规断开检测电路相比时，所公开的电路利用相对较低的电源电压来以更高的精度来检测高差分电压断开条件。