公开(公告)号：US09246509B1

公开(公告)日：2016-01-26

申请号：US14474945

申请日：2014-09-02

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Neha Bhargava ,  Ankur Bal

IPC: H03M3/02 ,  H03M3/00

CPC classification number: H03M3/412 ,  H03M1/145 ,  H03M1/68 ,  H03M3/382 ,  H03M3/424 ,  H03M3/458 ,  H03M3/464

Abstract: A sigma delta analog-to-digital converter includes a sigma delta modulator including a segmented digital-to-analog converter (DAC), the segmented DAC including a coarse DAC and a fine DAC, wherein the sigma delta modulator is configured to generate a coarse quantized signal and a fine quantized signal; recombination logic configured to combine the coarse quantized signal and the fine quantized signal; and a calibration circuit, operable in a calibration mode, to calibrate the recombination logic to compensate for mismatch between the coarse DAC and the fine DAC of the segmented DAC.

Abstract translation: Σ-Δ模数转换器包括包括分段数模转换器（DAC）的Σ-Δ调制器，分段DAC包括粗DAC和精细DAC，其中，Σ-Δ调制器被配置为产生粗 量化信号和精细量化信号; 复合逻辑，被配置为组合所述粗量化信号和所述精细量化信号; 以及可在校准模式下操作的校准电路，以校准复合逻辑以补偿分段DAC的粗DAC和精细DAC之间的失配。