公开(公告)号：US20030034821A1

公开(公告)日：2003-02-20

申请号：US09955926

申请日：2001-09-18

Applicant: STMicroelectronics S.A.

Inventor： Catherine Mallardeau ,  Pascale Mazoyer ,  Marc Piazza

IPC: G06F001/04

CPC classification number: H01L27/10852 ,  H01L27/10882 ,  H01L27/10888

Abstract: There is provided an integrated circuit having active components including junctions formed in a monocrystalline substrate doped locally, and at least one passive component situated above the active components. The integrated circuit includes a first insulating layer separating the active components and abase of the passive component, and a metal terminal for electrically connecting the passive component with at least one of the active components. The metal terminal is formed in the thickness of the first insulating layer and has a contact surface that projects from the limits of a junction of the one active component. In a preferred embodiment, the passive component is a capacitor. Also provided is a method of fabricating an integrated circuit that includes MOS transistors and an onboard memory plane of DRAM cells in a matrix.

Abstract translation: 提供了一种集成电路，其具有包括局部掺杂的单晶衬底中形成的结的活性组分和位于活性组分之上的至少一个无源组分。 集成电路包括分离有源部件的第一绝缘层和无源部件的放宽，以及用于将无源部件与至少一个有源部件电连接的金属端子。 金属端子形成为第一绝缘层的厚度，并且具有从一个有源部件的接合极限突出的接触表面。 在优选实施例中，无源部件是电容器。 还提供了一种制造集成电路的方法，该集成电路包括MOS晶体管和矩阵中的DRAM单元的板载存储器平面。

公开(公告)号：US20020110976A1

公开(公告)日：2002-08-15

申请号：US10042520

申请日：2002-01-08

Applicant: STMicroelectronics S.A.

Inventor： Philippe Coronel ,  Marc Piazza ,  Francois Leverd

IPC: H01L021/8242 ,  H01L021/4763 ,  H01L021/20

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: The invention relates to a DRAM integration method that does away with the alignment margins inherent to the photoetching step of the upper electrode of the capacitance for inserting the bit line contact. The removal of the upper electrode is self-aligned on the lower electrode of the capacitance. This is accomplished by forming a difference in topography at the point where the opening of the upper electrode is to be made, and depositing a non-doped polysilicon layer on the upper electrode. An implantation of dopants is performed on this layer, and the part of the non-doped layer located in the lower part of the zone showing the difference in topography is selectively etched. The remainder of the polysilicon layer and the part of the upper electrode located in the lower layer are also etched.

Abstract translation: 本发明涉及一种DRAM积分方法，其消除了用于插入位线接触的电容的上电极的光刻步骤固有的对准边缘。 上电极的去除在电容的下电极上自对准。 这是通过在要形成上电极的开口的位置处形成不同的形貌并在上电极上沉积非掺杂多晶硅层来实现的。 在该层上进行掺杂剂的注入，并且选择性地蚀刻位于显示区域差异的区域下部的非掺杂层的部分。 多晶硅层的剩余部分和位于下层的上部电极的一部分也被蚀刻。